ALERT_HANDLER Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: 042415198f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.038m	7.275ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.130s	37.411us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.340s	488.541us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.038m	24.796ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.084m	3.306ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.370s	112.450us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.340s	488.541us	20	20	100.00
		alert_handler_csr_aliasing	4.084m	3.306ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.633m	17.626ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.255m	4.637ms	50	50	100.00
V2	entropy	alert_handler_entropy	50.604m	56.214ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.012m	5.563ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.038m	7.275ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.035m	1.265ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.103m	1.181ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.652m	30.237ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.522m	58.554ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.778m	55.477ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.177h	152.257ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.022m	2.561ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.850s	82.512us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.190s	26.568us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.560s	296.356us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.560s	296.356us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.130s	37.411us	5	5	100.00
		alert_handler_csr_rw	10.340s	488.541us	20	20	100.00
		alert_handler_csr_aliasing	4.084m	3.306ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.440s	1.337ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.130s	37.411us	5	5	100.00
		alert_handler_csr_rw	10.340s	488.541us	20	20	100.00
		alert_handler_csr_aliasing	4.084m	3.306ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.440s	1.337ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	4.789m	18.288ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	4.789m	18.288ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	4.789m	18.288ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	4.789m	18.288ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.054m	63.046ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
		alert_handler_tl_intg_err	1.359m	4.983ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.359m	4.983ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	4.789m	18.288ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.038m	7.275ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.038m	7.275ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.038m	7.275ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.038m	7.275ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.012m	5.563ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.522m	58.554ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.012m	5.563ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	50.604m	56.214ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	50.604m	56.214ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.830s	509.684us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.031h	129.586ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			849	850	99.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.66	100.00	100.00	100.00	99.38	99.72

Failure Buckets

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 22.alert_handler_stress_all_with_rand_reset.6102604487535889236468949070004824611180891168062525860738727589501999644122
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e43350c6-c90f-436e-bd77-44f0f0892fee
      

Past Results

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