ALERT_HANDLER Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: cf38c1d296

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.129m	5.196ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.530s	111.141us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.330s	168.942us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.957m	8.936ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.260m	4.393ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.840s	89.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.330s	168.942us	20	20	100.00
		alert_handler_csr_aliasing	4.260m	4.393ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.248m	42.914ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.051m	9.329ms	50	50	100.00
V2	entropy	alert_handler_entropy	44.083m	65.950ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.027m	1.044ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.129m	5.196ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.181m	20.118ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	53.520s	927.833us	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.216m	70.664ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.367m	59.298ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.552m	95.036ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	58.401m	281.902ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.960s	1.389ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.290s	54.753us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.780s	55.337us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	17.910s	581.301us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	17.910s	581.301us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.530s	111.141us	5	5	100.00
		alert_handler_csr_rw	8.330s	168.942us	20	20	100.00
		alert_handler_csr_aliasing	4.260m	4.393ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.410s	1.109ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.530s	111.141us	5	5	100.00
		alert_handler_csr_rw	8.330s	168.942us	20	20	100.00
		alert_handler_csr_aliasing	4.260m	4.393ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.410s	1.109ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.700m	31.161ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.700m	31.161ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.700m	31.161ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.700m	31.161ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	17.021m	16.417ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
		alert_handler_tl_intg_err	1.302m	1.373ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.302m	1.373ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.700m	31.161ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.129m	5.196ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.129m	5.196ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.129m	5.196ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.129m	5.196ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.027m	1.044ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.367m	59.298ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.027m	1.044ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	44.083m	65.950ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	44.083m	65.950ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	29.740s	713.835us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.732h	130.170ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			847	850	99.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.69	100.00	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 1.alert_handler_sig_int_fail.59044545605026319317531716977520743245289035576121028965741534582771361672554
      Line 257, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 804503062 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (151 [0x97] vs 5 [0x5])
        UVM_INFO @ 804503062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 12.alert_handler_stress_all_with_rand_reset.11955403674428483219157501201489079280986933563505228684832257988174846216881
      Line 707, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21243796115 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 21243796115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* has 1 failures:

  • Test alert_handler_entropy has 1 failures.

    • 30.alert_handler_entropy.112996827056540018794377773888859688035843306575266132072431398217174145546479
      Line 255, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_entropy/latest/run.log

        UVM_ERROR @ 154554541927 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: alert_handler_reg_block.loc_alert_cause_0
        UVM_INFO @ 154554541927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2023.12.28_03.39.51
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