ALERT_HANDLER Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.226m 3.712ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 9.260s 103.579us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 8.920s 289.709us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 8.255m 17.452ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 5.403m 4.498ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 7.460s 276.277us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 8.920s 289.709us 20 20 100.00
alert_handler_csr_aliasing 5.403m 4.498ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 5.967m 25.576ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 59.460s 1.002ms 50 50 100.00
V2 entropy alert_handler_entropy 53.714m 200.730ms 48 50 96.00
V2 sig_int_fail alert_handler_sig_int_fail 1.117m 1.080ms 50 50 100.00
V2 clk_skew alert_handler_smoke 1.226m 3.712ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.224m 2.380ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.288m 1.264ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 11.333m 63.266ms 50 50 100.00
V2 lpg alert_handler_lpg 54.385m 54.139ms 48 50 96.00
alert_handler_lpg_stub_clk 58.844m 108.641ms 48 50 96.00
V2 stress_all alert_handler_stress_all 1.034h 372.684ms 50 50 100.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 55.850s 2.628ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.090s 51.875us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.700s 13.323us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 21.540s 1.114ms 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 21.540s 1.114ms 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 9.260s 103.579us 5 5 100.00
alert_handler_csr_rw 8.920s 289.709us 20 20 100.00
alert_handler_csr_aliasing 5.403m 4.498ms 5 5 100.00
alert_handler_same_csr_outstanding 43.410s 2.774ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 9.260s 103.579us 5 5 100.00
alert_handler_csr_rw 8.920s 289.709us 20 20 100.00
alert_handler_csr_aliasing 5.403m 4.498ms 5 5 100.00
alert_handler_same_csr_outstanding 43.410s 2.774ms 20 20 100.00
V2 TOTAL 624 630 99.05
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 6.453m 5.584ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 6.453m 5.584ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 6.453m 5.584ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 6.453m 5.584ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 24.359m 95.387ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
alert_handler_tl_intg_err 1.476m 13.827ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.476m 13.827ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 6.453m 5.584ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.226m 3.712ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.226m 3.712ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.226m 3.712ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.226m 3.712ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.117m 1.080ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 54.385m 54.139ms 48 50 96.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.117m 1.080ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 53.714m 200.730ms 48 50 96.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 53.714m 200.730ms 48 50 96.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 27.840s 486.932us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.651h 1.106s 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 843 850 99.18

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 12 80.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.66 99.99 98.71 100.00 100.00 100.00 99.30 99.60

Failure Buckets

Past Results