ALERT_HANDLER Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.316m	5.089ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.110s	661.282us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.260s	204.846us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.082m	8.939ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.011m	3.906ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.480s	272.000us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.260s	204.846us	20	20	100.00
		alert_handler_csr_aliasing	4.011m	3.906ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.100m	20.609ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.186m	1.275ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.925m	107.262ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.286m	2.237ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.316m	5.089ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.311m	5.168ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.281m	8.898ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.464m	78.004ms	50	50	100.00
V2	lpg	alert_handler_lpg	49.283m	202.958ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.823m	631.101ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.219h	302.538ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	38.370s	937.903us	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.340s	785.258us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.950s	23.185us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	23.430s	730.758us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	23.430s	730.758us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.110s	661.282us	5	5	100.00
		alert_handler_csr_rw	10.260s	204.846us	20	20	100.00
		alert_handler_csr_aliasing	4.011m	3.906ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.350s	3.970ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.110s	661.282us	5	5	100.00
		alert_handler_csr_rw	10.260s	204.846us	20	20	100.00
		alert_handler_csr_aliasing	4.011m	3.906ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.350s	3.970ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.337m	5.503ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.337m	5.503ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.337m	5.503ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.337m	5.503ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.995m	18.571ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
		alert_handler_tl_intg_err	1.303m	1.414ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.303m	1.414ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.337m	5.503ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.316m	5.089ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.316m	5.089ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.316m	5.089ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.316m	5.089ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.286m	2.237ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	49.283m	202.958ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.286m	2.237ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.925m	107.262ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.925m	107.262ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	47.430s	1.122ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.803h	766.263ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			847	850	99.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.65	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 23.alert_handler_stress_all_with_rand_reset.106173585984772676615168386064465266153958845363297889307168172770423726895858
      Line 638, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69110922933 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 69110922933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 24.alert_handler_sig_int_fail.2893920665689922968221937171996397509228173702385244680444339634439041423378
      Line 255, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  43592959 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @  43592959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 25.alert_handler_stress_all.98134063290866392782854054837564577123390262238193786596072443876920971005657
      Line 255, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_stress_all/latest/run.log

        UVM_ERROR @  91204615 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (185 [0xb9] vs 425 [0x1a9])
        UVM_INFO @  91204615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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