ALERT_HANDLER Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.164m	1.220ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.020s	522.850us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.890s	124.823us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.429m	16.442ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.855m	4.732ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.110s	74.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.890s	124.823us	20	20	100.00
		alert_handler_csr_aliasing	2.855m	4.732ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.212m	23.275ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.319m	2.782ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.469m	103.723ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.099m	9.642ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.164m	1.220ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.189m	4.653ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.372m	4.162ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.792m	73.341ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.681m	171.206ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.008m	193.864ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.352h	159.169ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	39.700s	10.087ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.350s	197.563us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.850s	17.566us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.660s	328.836us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.660s	328.836us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.020s	522.850us	5	5	100.00
		alert_handler_csr_rw	9.890s	124.823us	20	20	100.00
		alert_handler_csr_aliasing	2.855m	4.732ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.260s	2.707ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.020s	522.850us	5	5	100.00
		alert_handler_csr_rw	9.890s	124.823us	20	20	100.00
		alert_handler_csr_aliasing	2.855m	4.732ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.260s	2.707ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.462m	11.346ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.462m	11.346ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.462m	11.346ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.462m	11.346ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.177m	66.349ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
		alert_handler_tl_intg_err	1.541m	2.556ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.541m	2.556ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.462m	11.346ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.164m	1.220ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.164m	1.220ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.164m	1.220ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.164m	1.220ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.099m	9.642ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.681m	171.206ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.099m	9.642ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.469m	103.723ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.469m	103.723ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.540s	6.352ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.803h	452.736ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			850	850	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.67	99.97	100.00	100.00	99.38	99.56

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