ALERT_HANDLER Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.163m 19.621ms 49 50 98.00
V1 csr_hw_reset alert_handler_csr_hw_reset 10.000s 133.832us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 10.140s 124.183us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 8.884m 8.559ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 4.907m 17.186ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 7.240s 78.685us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 10.140s 124.183us 20 20 100.00
alert_handler_csr_aliasing 4.907m 17.186ms 5 5 100.00
V1 TOTAL 104 105 99.05
V2 esc_accum alert_handler_esc_alert_accum 6.175m 13.041ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.095m 4.181ms 49 50 98.00
V2 entropy alert_handler_entropy 54.470m 57.124ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.216m 1.206ms 49 50 98.00
V2 clk_skew alert_handler_smoke 1.163m 19.621ms 49 50 98.00
V2 random_alerts alert_handler_random_alerts 1.172m 1.065ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.271m 2.908ms 49 50 98.00
V2 ping_timeout alert_handler_ping_timeout 11.655m 167.697ms 49 50 98.00
V2 lpg alert_handler_lpg 52.044m 209.239ms 49 50 98.00
alert_handler_lpg_stub_clk 57.413m 57.432ms 48 50 96.00
V2 stress_all alert_handler_stress_all 1.140h 75.192ms 50 50 100.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 2.446m 3.595ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 3.970s 48.827us 20 20 100.00
V2 intr_test alert_handler_intr_test 2.940s 49.728us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 27.520s 1.606ms 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 27.520s 1.606ms 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 10.000s 133.832us 5 5 100.00
alert_handler_csr_rw 10.140s 124.183us 20 20 100.00
alert_handler_csr_aliasing 4.907m 17.186ms 5 5 100.00
alert_handler_same_csr_outstanding 46.800s 5.038ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 10.000s 133.832us 5 5 100.00
alert_handler_csr_rw 10.140s 124.183us 20 20 100.00
alert_handler_csr_aliasing 4.907m 17.186ms 5 5 100.00
alert_handler_same_csr_outstanding 46.800s 5.038ms 20 20 100.00
V2 TOTAL 623 630 98.89
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 6.109m 23.305ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 6.109m 23.305ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 6.109m 23.305ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 6.109m 23.305ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 18.331m 15.545ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
alert_handler_tl_intg_err 1.176m 2.726ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.176m 2.726ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 6.109m 23.305ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.163m 19.621ms 49 50 98.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.163m 19.621ms 49 50 98.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.163m 19.621ms 49 50 98.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.163m 19.621ms 49 50 98.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.216m 1.206ms 49 50 98.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 52.044m 209.239ms 49 50 98.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.216m 1.206ms 49 50 98.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 54.470m 57.124ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 54.470m 57.124ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 25.370s 1.694ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.356h 155.091ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 840 850 98.82

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 15 15 9 60.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.64 99.99 98.69 99.97 100.00 100.00 99.38 99.48

Failure Buckets

Past Results