17d5a97c3b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | alert_handler_smoke | 1.163m | 19.621ms | 49 | 50 | 98.00 |
V1 | csr_hw_reset | alert_handler_csr_hw_reset | 10.000s | 133.832us | 5 | 5 | 100.00 |
V1 | csr_rw | alert_handler_csr_rw | 10.140s | 124.183us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.884m | 8.559ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | alert_handler_csr_aliasing | 4.907m | 17.186ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 7.240s | 78.685us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 10.140s | 124.183us | 20 | 20 | 100.00 |
alert_handler_csr_aliasing | 4.907m | 17.186ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 104 | 105 | 99.05 | |||
V2 | esc_accum | alert_handler_esc_alert_accum | 6.175m | 13.041ms | 50 | 50 | 100.00 |
V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.095m | 4.181ms | 49 | 50 | 98.00 |
V2 | entropy | alert_handler_entropy | 54.470m | 57.124ms | 50 | 50 | 100.00 |
V2 | sig_int_fail | alert_handler_sig_int_fail | 1.216m | 1.206ms | 49 | 50 | 98.00 |
V2 | clk_skew | alert_handler_smoke | 1.163m | 19.621ms | 49 | 50 | 98.00 |
V2 | random_alerts | alert_handler_random_alerts | 1.172m | 1.065ms | 50 | 50 | 100.00 |
V2 | random_classes | alert_handler_random_classes | 1.271m | 2.908ms | 49 | 50 | 98.00 |
V2 | ping_timeout | alert_handler_ping_timeout | 11.655m | 167.697ms | 49 | 50 | 98.00 |
V2 | lpg | alert_handler_lpg | 52.044m | 209.239ms | 49 | 50 | 98.00 |
alert_handler_lpg_stub_clk | 57.413m | 57.432ms | 48 | 50 | 96.00 | ||
V2 | stress_all | alert_handler_stress_all | 1.140h | 75.192ms | 50 | 50 | 100.00 |
V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 2.446m | 3.595ms | 20 | 20 | 100.00 |
V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 3.970s | 48.827us | 20 | 20 | 100.00 |
V2 | intr_test | alert_handler_intr_test | 2.940s | 49.728us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 27.520s | 1.606ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | alert_handler_tl_errors | 27.520s | 1.606ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 10.000s | 133.832us | 5 | 5 | 100.00 |
alert_handler_csr_rw | 10.140s | 124.183us | 20 | 20 | 100.00 | ||
alert_handler_csr_aliasing | 4.907m | 17.186ms | 5 | 5 | 100.00 | ||
alert_handler_same_csr_outstanding | 46.800s | 5.038ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 10.000s | 133.832us | 5 | 5 | 100.00 |
alert_handler_csr_rw | 10.140s | 124.183us | 20 | 20 | 100.00 | ||
alert_handler_csr_aliasing | 4.907m | 17.186ms | 5 | 5 | 100.00 | ||
alert_handler_same_csr_outstanding | 46.800s | 5.038ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 623 | 630 | 98.89 | |||
V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.109m | 23.305ms | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.109m | 23.305ms | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.109m | 23.305ms | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.109m | 23.305ms | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 18.331m | 15.545ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
alert_handler_tl_intg_err | 1.176m | 2.726ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.176m | 2.726ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.109m | 23.305ms | 20 | 20 | 100.00 |
V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.163m | 19.621ms | 49 | 50 | 98.00 |
V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.163m | 19.621ms | 49 | 50 | 98.00 |
V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.163m | 19.621ms | 49 | 50 | 98.00 |
V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.163m | 19.621ms | 49 | 50 | 98.00 |
V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.216m | 1.206ms | 49 | 50 | 98.00 |
V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 52.044m | 209.239ms | 49 | 50 | 98.00 |
V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.216m | 1.206ms | 49 | 50 | 98.00 |
V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 54.470m | 57.124ms | 50 | 50 | 100.00 |
V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 54.470m | 57.124ms | 50 | 50 | 100.00 |
V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 25.370s | 1.694ms | 5 | 5 | 100.00 |
V2S | TOTAL | 65 | 65 | 100.00 | |||
V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.356h | 155.091ms | 48 | 50 | 96.00 |
V3 | TOTAL | 48 | 50 | 96.00 | |||
TOTAL | 840 | 850 | 98.82 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 5 | 83.33 |
V2 | 15 | 15 | 9 | 60.00 |
V2S | 4 | 4 | 4 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.64 | 99.99 | 98.69 | 99.97 | 100.00 | 100.00 | 99.38 | 99.48 |
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 3 failures:
Test alert_handler_lpg_stub_clk has 2 failures.
14.alert_handler_lpg_stub_clk.8444225076839876347376094143166036314838098428205191648826406960728690295894
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:43b1dc6d-75c4-468e-bef3-2723221f8080
26.alert_handler_lpg_stub_clk.9254584129505257883219229323910475694829379653217608421862176782262532723611
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:b0765b3b-7886-459b-aa73-2159fe652264
Test alert_handler_random_classes has 1 failures.
15.alert_handler_random_classes.35627388640590285846122125724659755443642239296721241671474173314493627009903
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_random_classes/latest/run.log
Job ID: smart:6aad8b67-a85a-413a-8ad6-9a8117969ac3
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found
has 1 failures:
0.alert_handler_lpg.45873351566931977211522055854566227583057475501008724322636301755007589409854
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_lpg/latest/run.log
Job ID: smart:538bc8a4-b82d-4124-81a7-358fb9a56b7d
Exit reason: Error: User command failed Job returned non-zero exit code
has 1 failures:
6.alert_handler_sig_int_fail.91971455888076842902984902360026057277503091645515929468578480167017628894153
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest/run.log
[make]: simulate
cd /workspace/6.alert_handler_sig_int_fail/latest && /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957916617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3957916617
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 24 13:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 1 failures:
8.alert_handler_ping_timeout.11768678506151664488397900409923173462673071586212652611021665038655975997160
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest/run.log
Job ID: smart:7ca326d4-3bf9-4459-a1d1-3c78798f32ae
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 1 failures:
11.alert_handler_esc_intr_timeout.107529697679106010621976064386239257964544399050885077738865215204176252970360
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest/run.log
Job ID: smart:0024a87a-0b63-4c31-a0ff-6a869773d9aa
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 1 failures:
16.alert_handler_smoke.69773799803695585232142634017172945156803400640628657528698391219731990235567
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_smoke/latest/run.log
Job ID: smart:1b175680-73c3-479b-9cc3-30b9e6a11ee2
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
25.alert_handler_stress_all_with_rand_reset.99243035177501496242986042155316377213031464072293275138525252661541774091090
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest/run.log
Job ID: smart:01367fb4-a92f-45e0-b2f7-52a45121dce3
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail
has 1 failures:
46.alert_handler_stress_all_with_rand_reset.13564354516530903094097869022406429156115175815159630182549276803561901990485
Line 1061, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 158746306405 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 158746306405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---