4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | alert_handler_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 0 | 20 | 0.00 | ||
| alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 0 | 50 | 0.00 | ||
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 0 | 50 | 0.00 | ||
| V2 | entropy | alert_handler_entropy | 0 | 50 | 0.00 | ||
| V2 | sig_int_fail | alert_handler_sig_int_fail | 0 | 50 | 0.00 | ||
| V2 | clk_skew | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2 | random_alerts | alert_handler_random_alerts | 0 | 50 | 0.00 | ||
| V2 | random_classes | alert_handler_random_classes | 0 | 50 | 0.00 | ||
| V2 | ping_timeout | alert_handler_ping_timeout | 0 | 50 | 0.00 | ||
| V2 | lpg | alert_handler_lpg | 0 | 50 | 0.00 | ||
| alert_handler_lpg_stub_clk | 0 | 50 | 0.00 | ||||
| V2 | stress_all | alert_handler_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 0 | 20 | 0.00 | ||
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 0 | 20 | 0.00 | ||
| V2 | intr_test | alert_handler_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 0 | 5 | 0.00 | ||
| alert_handler_csr_rw | 0 | 20 | 0.00 | ||||
| alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||||
| alert_handler_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 0 | 5 | 0.00 | ||
| alert_handler_csr_rw | 0 | 20 | 0.00 | ||||
| alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||||
| alert_handler_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 630 | 0.00 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| alert_handler_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 65 | 0.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 850 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 15 | 15 | 0 | 0.00 |
| V2S | 4 | 4 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 852 failures:
0.alert_handler_smoke.39876923838949610186173895910318592721208134068041079200772035315057999600485
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_smoke/latest/run.log
1.alert_handler_smoke.107239745404014913216600857748893623048740444025088476310090813288938410365108
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_smoke/latest/run.log
... and 48 more failures.
0.alert_handler_random_alerts.32531055940485588299413681326204444311325309417606121009624728425564415920531
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest/run.log
1.alert_handler_random_alerts.93844796952262636426576889321723186721995347944306286190184984727302095862303
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest/run.log
... and 48 more failures.
0.alert_handler_random_classes.31676994841462722301002767926604154107623269325775717501952357270096135980382
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_random_classes/latest/run.log
1.alert_handler_random_classes.64584694622770010633718087181022129504061478718753036747324946153156959943141
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_random_classes/latest/run.log
... and 48 more failures.
0.alert_handler_esc_intr_timeout.83016259494692399794372442424973908640508132751412034564679280982400400135022
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest/run.log
1.alert_handler_esc_intr_timeout.27167721306772022633923032327365654038261668534595358585276761057793119091880
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest/run.log
... and 48 more failures.
0.alert_handler_esc_alert_accum.97287370365160253636747849471950143121407055509653607991959344211779657791916
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest/run.log
1.alert_handler_esc_alert_accum.77140964286098942554950685912751984228142540754720669648833898088975863025042
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.