ALERT_HANDLER Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.189m	2.864ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.650s	334.017us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.400s	519.094us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.918m	5.825ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.929m	3.736ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.240s	70.518us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.400s	519.094us	20	20	100.00
		alert_handler_csr_aliasing	3.929m	3.736ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.651m	9.289ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.353m	5.357ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.536m	226.211ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.249m	5.081ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.189m	2.864ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.045m	884.857us	50	50	100.00
V2	random_classes	alert_handler_random_classes	58.070s	968.902us	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.781m	65.828ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.794m	57.447ms	50	50	100.00
		alert_handler_lpg_stub_clk	50.955m	188.894ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.140h	140.704ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	55.620s	11.264ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.170s	329.102us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.850s	47.687us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.560s	340.113us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.560s	340.113us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.650s	334.017us	5	5	100.00
		alert_handler_csr_rw	9.400s	519.094us	20	20	100.00
		alert_handler_csr_aliasing	3.929m	3.736ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.830s	517.304us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.650s	334.017us	5	5	100.00
		alert_handler_csr_rw	9.400s	519.094us	20	20	100.00
		alert_handler_csr_aliasing	3.929m	3.736ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.830s	517.304us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.265m	8.427ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.265m	8.427ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.265m	8.427ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.265m	8.427ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.330m	63.563ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
		alert_handler_tl_intg_err	1.165m	1.055ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.165m	1.055ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.265m	8.427ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.189m	2.864ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.189m	2.864ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.189m	2.864ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.189m	2.864ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.249m	5.081ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.794m	57.447ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.249m	5.081ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.536m	226.211ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.536m	226.211ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	49.490s	1.123ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.872h	156.152ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			848	850	99.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.67	100.00	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 0.alert_handler_sig_int_fail.30644315529783432936548918385277993716720565128880665766714543982635133990167
      Line 417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 124043777 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 124043777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 21.alert_handler_stress_all_with_rand_reset.30230909180891064945483876343927895834918935761739092531303245183309586476489
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:82f106f9-a71d-490d-a011-03e039578794
      

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