ALERT_HANDLER Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.252m	2.423ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	7.920s	375.415us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.400s	524.308us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.920m	29.648ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.078m	13.213ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.850s	144.329us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.400s	524.308us	20	20	100.00
		alert_handler_csr_aliasing	4.078m	13.213ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.692m	6.145ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.220m	1.191ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.359m	120.654ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.128m	1.192ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.252m	2.423ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.268m	2.344ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.262m	4.497ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.433m	30.152ms	50	50	100.00
V2	lpg	alert_handler_lpg	44.979m	99.824ms	50	50	100.00
		alert_handler_lpg_stub_clk	50.481m	214.934ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.276h	80.013ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	56.010s	2.579ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.490s	55.015us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.700s	10.892us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.930s	1.314ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.930s	1.314ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	7.920s	375.415us	5	5	100.00
		alert_handler_csr_rw	9.400s	524.308us	20	20	100.00
		alert_handler_csr_aliasing	4.078m	13.213ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.660s	659.178us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	7.920s	375.415us	5	5	100.00
		alert_handler_csr_rw	9.400s	524.308us	20	20	100.00
		alert_handler_csr_aliasing	4.078m	13.213ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.660s	659.178us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.200m	22.487ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.200m	22.487ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.200m	22.487ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.200m	22.487ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.762m	69.689ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
		alert_handler_tl_intg_err	1.171m	1.107ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.171m	1.107ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.200m	22.487ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.252m	2.423ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.252m	2.423ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.252m	2.423ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.252m	2.423ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.128m	1.192ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	44.979m	99.824ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.128m	1.192ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.359m	120.654ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.359m	120.654ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	59.700s	1.338ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.592h	588.045ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			848	850	99.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.69	99.99	98.71	100.00	100.00	100.00	99.38	99.76

Failure Buckets

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 27.alert_handler_stress_all_with_rand_reset.71375927704683550557089064947875126163162381570959028791588482570147713151711
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:8014c932-6ae3-4bd8-b49d-52662ca4db38
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 28.alert_handler_stress_all.97714206671253552887481284819308288123032024208459956176258676015789592197477
      Line 59381, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 168043120169 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 168043120169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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