93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | alert_handler_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 0 | 20 | 0.00 | ||
| alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 0 | 50 | 0.00 | ||
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 0 | 50 | 0.00 | ||
| V2 | entropy | alert_handler_entropy | 0 | 50 | 0.00 | ||
| V2 | sig_int_fail | alert_handler_sig_int_fail | 0 | 50 | 0.00 | ||
| V2 | clk_skew | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2 | random_alerts | alert_handler_random_alerts | 0 | 50 | 0.00 | ||
| V2 | random_classes | alert_handler_random_classes | 0 | 50 | 0.00 | ||
| V2 | ping_timeout | alert_handler_ping_timeout | 0 | 50 | 0.00 | ||
| V2 | lpg | alert_handler_lpg | 0 | 50 | 0.00 | ||
| alert_handler_lpg_stub_clk | 0 | 50 | 0.00 | ||||
| V2 | stress_all | alert_handler_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 0 | 20 | 0.00 | ||
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 0 | 20 | 0.00 | ||
| V2 | intr_test | alert_handler_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 0 | 5 | 0.00 | ||
| alert_handler_csr_rw | 0 | 20 | 0.00 | ||||
| alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||||
| alert_handler_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 0 | 5 | 0.00 | ||
| alert_handler_csr_rw | 0 | 20 | 0.00 | ||||
| alert_handler_csr_aliasing | 0 | 5 | 0.00 | ||||
| alert_handler_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 630 | 0.00 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| alert_handler_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 0 | 50 | 0.00 | ||
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 65 | 0.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 850 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 15 | 15 | 0 | 0.00 |
| V2S | 4 | 4 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 852 failures:
0.alert_handler_smoke.102609954944613061036360948437292057708814736234941443487574180855819089072612
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_smoke/latest/run.log
1.alert_handler_smoke.81455385039305973744868375307880568071740876718953624265664347551675362510795
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_smoke/latest/run.log
... and 48 more failures.
0.alert_handler_random_alerts.87684865548818026409377528641707912934345810615452658180067397838247534270504
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest/run.log
1.alert_handler_random_alerts.80545437550412071387490988982929894511200259399834273843973421758766648513081
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest/run.log
... and 48 more failures.
0.alert_handler_random_classes.2775602015061695636952546507364699833250749069461671811921518370656106455573
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_random_classes/latest/run.log
1.alert_handler_random_classes.93967849754207483100778045535854633779684466666978877056906641640460639189658
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_random_classes/latest/run.log
... and 48 more failures.
0.alert_handler_esc_intr_timeout.109962730398195747972741201096442697413594869022451581937219182246798013640947
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest/run.log
1.alert_handler_esc_intr_timeout.45504998432304406052673563218090593657066392004724464756599856494695463809341
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest/run.log
... and 48 more failures.
0.alert_handler_esc_alert_accum.13367323963015725471150365725441386321983542886534929485430740749559894521323
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest/run.log
1.alert_handler_esc_alert_accum.110898889088911447374862476582281751312179542606234440257280454107448825977835
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest/run.log
... and 48 more failures.
Job alert_handler-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/default/build.log
Job ID: smart:e7ee6fd0-f5b5-4614-bb87-e895c41e8ddf
Job alert_handler-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/build.log
Job ID: smart:ff6bf895-62a1-4edd-8adc-7f1f532fbc57