ALERT_HANDLER Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.084m	1.850ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.340s	439.255us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.310s	472.109us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.691m	8.926ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.872m	17.616ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	20.010s	176.656us	7	20	35.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.310s	472.109us	20	20	100.00
		alert_handler_csr_aliasing	4.872m	17.616ms	5	5	100.00
V1		TOTAL			92	105	87.62
V2	esc_accum	alert_handler_esc_alert_accum	4.287m	9.440ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.255m	4.641ms	50	50	100.00
V2	entropy	alert_handler_entropy	48.403m	101.404ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.163m	2.428ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.084m	1.850ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.291m	2.649ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.098m	5.240ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.120m	17.469ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.407m	111.402ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.535m	56.250ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.071h	67.348ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	36.890s	2.232ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.450s	54.038us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.810s	15.582us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	29.740s	1.062ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	29.740s	1.062ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.340s	439.255us	5	5	100.00
		alert_handler_csr_rw	10.310s	472.109us	20	20	100.00
		alert_handler_csr_aliasing	4.872m	17.616ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.690s	702.064us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.340s	439.255us	5	5	100.00
		alert_handler_csr_rw	10.310s	472.109us	20	20	100.00
		alert_handler_csr_aliasing	4.872m	17.616ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.690s	702.064us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.966m	24.904ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.966m	24.904ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.966m	24.904ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.966m	24.904ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.873m	33.790ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
		alert_handler_tl_intg_err	1.502m	2.388ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.502m	2.388ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.966m	24.904ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.084m	1.850ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.084m	1.850ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.084m	1.850ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.084m	1.850ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.163m	2.428ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.407m	111.402ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.163m	2.428ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	48.403m	101.404ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	48.403m	101.404ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.940s	542.433us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.197h	81.020ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			804	850	94.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.72	99.97	100.00	100.00	99.38	99.40

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 44 failures:
- Test alert_handler_csr_mem_rw_with_rand_reset has 13 failures.
  - 0.alert_handler_csr_mem_rw_with_rand_reset.112032794917382721171213112587808905557050658621857521688648798230441993761884
    Line 255, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109837029 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 109837029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.alert_handler_csr_mem_rw_with_rand_reset.17125180311468124581739033174481981032215313174068946232164708466754053832045
    Line 330, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 213125062 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 213125062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
- Test alert_handler_stress_all_with_rand_reset has 31 failures.
  - 1.alert_handler_stress_all_with_rand_reset.66453206437677192791091547262436622711758593551863229504205751995156577188841
    Line 5224, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8446574933 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 8446574933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.36947353976692114809690718845370133541635498174149532534941946055206618821599
    Line 54007, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45261644881 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 45261644881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 23.alert_handler_stress_all.79964227507716062408558041666751361999504595128187183389434637558689917173948
    Line 84139, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 649139510018 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 649139510018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 36.alert_handler_lpg_stub_clk.22158277365318727739665380993307880144748711002333273490324605473644367738851
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest/run.log
```
  Job ID: smart:ed780e9d-0248-4f0e-b6c9-d26e0b22ed2f
```

ALERT_HANDLER Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8faf04697a`