ALERT_HANDLER Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.238m	2.575ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.090s	75.392us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.920s	346.626us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.586m	171.003ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.736m	25.847ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.310s	568.550us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.920s	346.626us	20	20	100.00
		alert_handler_csr_aliasing	4.736m	25.847ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.942m	5.345ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.152m	1.201ms	50	50	100.00
V2	entropy	alert_handler_entropy	46.952m	142.043ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	59.480s	2.342ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.238m	2.575ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.242m	2.548ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.038m	4.054ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.354m	29.669ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.415m	415.236ms	50	50	100.00
		alert_handler_lpg_stub_clk	51.565m	209.845ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.087h	486.443ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	58.840s	8.632ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.960s	38.401us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.910s	22.467us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.910s	451.732us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.910s	451.732us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.090s	75.392us	5	5	100.00
		alert_handler_csr_rw	8.920s	346.626us	20	20	100.00
		alert_handler_csr_aliasing	4.736m	25.847ms	5	5	100.00
		alert_handler_same_csr_outstanding	40.750s	661.390us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.090s	75.392us	5	5	100.00
		alert_handler_csr_rw	8.920s	346.626us	20	20	100.00
		alert_handler_csr_aliasing	4.736m	25.847ms	5	5	100.00
		alert_handler_same_csr_outstanding	40.750s	661.390us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.564m	5.452ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.564m	5.452ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.564m	5.452ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.564m	5.452ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	16.437m	46.559ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
		alert_handler_tl_intg_err	1.140m	4.397ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.140m	4.397ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.564m	5.452ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.238m	2.575ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.238m	2.575ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.238m	2.575ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.238m	2.575ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	59.480s	2.342ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.415m	415.236ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	59.480s	2.342ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	46.952m	142.043ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	46.952m	142.043ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	48.600s	2.617ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.966h	552.767ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.69	100.00	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:774) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 18 failures:
  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 0.alert_handler_stress_all_with_rand_reset.34275161294389780993452814780978837935815668816544646243125326670693163543296
      Line 40049, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7543163501 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 7543163501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.58339876444672010258367721439883304460653423409757693952079812354836962416544
      Line 21681, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 79420882887 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 79420882887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_vseq.sv:719) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 18.alert_handler_stress_all_with_rand_reset.17057774636659828439929470408333070408099804184108245415799447916996234378097
      Line 70151, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 154620109486 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 154620109486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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