ALERT_HANDLER Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	54.110s	8.818ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.220s	98.368us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.250s	142.137us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.127m	25.901ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.184m	28.359ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.370s	216.737us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.250s	142.137us	20	20	100.00
		alert_handler_csr_aliasing	2.184m	28.359ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.125m	22.715ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.174m	4.732ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.477m	63.013ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	59.510s	2.798ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	54.110s	8.818ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.116m	2.267ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.354m	5.200ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.818m	73.055ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.302m	244.376ms	50	50	100.00
		alert_handler_lpg_stub_clk	51.002m	218.651ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.131h	253.196ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	2.029m	16.511ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.290s	50.593us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.180s	27.790us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.000s	1.327ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.000s	1.327ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.220s	98.368us	5	5	100.00
		alert_handler_csr_rw	10.250s	142.137us	20	20	100.00
		alert_handler_csr_aliasing	2.184m	28.359ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.260s	691.370us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.220s	98.368us	5	5	100.00
		alert_handler_csr_rw	10.250s	142.137us	20	20	100.00
		alert_handler_csr_aliasing	2.184m	28.359ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.260s	691.370us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.820m	6.783ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.820m	6.783ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.820m	6.783ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.820m	6.783ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.697m	25.255ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
		alert_handler_tl_intg_err	1.264m	2.099ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.264m	2.099ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.820m	6.783ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	54.110s	8.818ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	54.110s	8.818ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	54.110s	8.818ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	54.110s	8.818ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	59.510s	2.798ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.302m	244.376ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	59.510s	2.798ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.477m	63.013ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.477m	63.013ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	48.300s	2.164ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.992h	124.086ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			836	850	98.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.66	100.00	100.00	100.00	99.38	99.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:774) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 11 failures:

  • Test alert_handler_stress_all_with_rand_reset has 11 failures.

    • 0.alert_handler_stress_all_with_rand_reset.80436775926349500997936602679905338021407844573593670817748521893736712122965
      Line 12386, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17405190142 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 17405190142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.alert_handler_stress_all_with_rand_reset.45928756593596854995817073473680632242082083876103337482999358769072119569992
      Line 10007, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9485332399 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 9485332399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (cip_base_vseq.sv:719) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 35.alert_handler_stress_all_with_rand_reset.44332288384060909760870064373997306638894127291588104052420238028369529098071
      Line 59991, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48941792025 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 48941792025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.alert_handler_stress_all_with_rand_reset.19159115891704713452609019891491304561098309895625488066998131781751717920310
      Line 7342, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14149659509 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 14149659509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 2.alert_handler_stress_all_with_rand_reset.51390693112932274773976550112643524458686299722407661825352342852262576212573
      Line 99449, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111751495704 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 6 [0x6]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 111751495704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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