ALERT_HANDLER Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.128m	2.083ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.780s	1.333ms	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.210s	445.088us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.716m	22.863ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.012m	13.087ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.110s	153.728us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.210s	445.088us	20	20	100.00
		alert_handler_csr_aliasing	4.012m	13.087ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.597m	86.599ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.227m	5.182ms	50	50	100.00
V2	entropy	alert_handler_entropy	44.879m	94.626ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.129m	8.384ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.128m	2.083ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.150m	986.054us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.135m	4.344ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.884m	30.099ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.896m	381.559ms	49	50	98.00
		alert_handler_lpg_stub_clk	58.957m	215.751ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.293h	80.891ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.008m	5.449ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.970s	45.743us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.930s	20.436us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.490s	559.964us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.490s	559.964us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.780s	1.333ms	5	5	100.00
		alert_handler_csr_rw	11.210s	445.088us	20	20	100.00
		alert_handler_csr_aliasing	4.012m	13.087ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.860s	660.152us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.780s	1.333ms	5	5	100.00
		alert_handler_csr_rw	11.210s	445.088us	20	20	100.00
		alert_handler_csr_aliasing	4.012m	13.087ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.860s	660.152us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.769m	8.677ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.769m	8.677ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.769m	8.677ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.769m	8.677ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.910m	307.624ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
		alert_handler_tl_intg_err	1.547m	2.698ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.547m	2.698ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.769m	8.677ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.128m	2.083ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.128m	2.083ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.128m	2.083ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.128m	2.083ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.129m	8.384ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.896m	381.559ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.129m	8.384ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	44.879m	94.626ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	44.879m	94.626ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	56.610s	3.329ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	1.982h	374.585ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.69	99.97	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:788) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test alert_handler_stress_all_with_rand_reset has 14 failures.

    • 0.alert_handler_stress_all_with_rand_reset.115385833621015764320287374586067499522676402132617202585173199989529840285187
      Line 19046, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24391730795 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24391730795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.24084392998106910684373898346085040702402507985618804812047219019857020479961
      Line 26242, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 230312227267 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 230312227267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_lpg has 1 failures.

    • 1.alert_handler_lpg.17172572078671846172326814694681460308778702494807115234724390993735307196275
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_lpg/latest/run.log

        Job ID: smart:9b5d21c2-e795-41f6-8613-3bac13a712e8
      

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 16.alert_handler_stress_all_with_rand_reset.59446052322916185891975167632996733435394497892696911354316366881040027215332
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7ac05837-ba7f-4aa1-bfbc-b9fa1d8c2849
      

• UVM_ERROR (cip_base_vseq.sv:719) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 11.alert_handler_stress_all_with_rand_reset.22329831955546030402814585433561546824546666069208534537997363305093380215108
      Line 54846, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107644309343 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 107644309343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.alert_handler_stress_all_with_rand_reset.83404076373030815528825342079577355331529068385879588184747547666941520844576
      Line 37306, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15227442369 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 15227442369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 46.alert_handler_stress_all_with_rand_reset.73049737947686738437129810940603773875757725413623572601458368924286406523959
      Line 43777, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 132904937898 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 132904937898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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