ALERT_HANDLER Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.119m	2.232ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.550s	129.994us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.420s	502.045us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.572m	11.652ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.819m	58.215ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.670s	793.590us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.420s	502.045us	20	20	100.00
		alert_handler_csr_aliasing	4.819m	58.215ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.472m	24.953ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.253m	4.457ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.961m	228.445ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.047m	8.023ms	47	50	94.00
V2	clk_skew	alert_handler_smoke	1.119m	2.232ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.124m	3.914ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.239m	9.278ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.031m	29.728ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.391m	118.279ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.178m	57.038ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.096h	1.111s	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	58.400s	5.470ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.400s	50.031us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.750s	15.393us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	33.120s	480.545us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	33.120s	480.545us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.550s	129.994us	5	5	100.00
		alert_handler_csr_rw	10.420s	502.045us	20	20	100.00
		alert_handler_csr_aliasing	4.819m	58.215ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.610s	1.352ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.550s	129.994us	5	5	100.00
		alert_handler_csr_rw	10.420s	502.045us	20	20	100.00
		alert_handler_csr_aliasing	4.819m	58.215ms	5	5	100.00
		alert_handler_same_csr_outstanding	43.610s	1.352ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.725m	5.538ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.725m	5.538ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.725m	5.538ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.725m	5.538ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.670m	64.326ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
		alert_handler_tl_intg_err	1.349m	1.319ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.349m	1.319ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.725m	5.538ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.119m	2.232ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.119m	2.232ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.119m	2.232ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.119m	2.232ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.047m	8.023ms	47	50	94.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.391m	118.279ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.047m	8.023ms	47	50	94.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.961m	228.445ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.961m	228.445ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.500s	584.522us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.583h	85.635ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			826	850	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.66	100.00	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:815) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test alert_handler_stress_all_with_rand_reset has 18 failures.
  - 2.alert_handler_stress_all_with_rand_reset.71139666922681994222212467201397621492676708183875955863147662974668601112247
    Line 7351, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9153944247 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9153944247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.alert_handler_stress_all_with_rand_reset.7017796055654301969173865027265748893719402979365510111457439055802158170463
    Line 31398, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 142327330632 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 142327330632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 0.alert_handler_stress_all_with_rand_reset.15196300270970662300838843921957928531494905834587552207371820569208902991071
    Line 15002, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 71424899293 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (46 [0x2e] vs 47 [0x2f]) reg name: alert_handler_reg_block.classb_accum_cnt
  UVM_INFO @ 71424899293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 20.alert_handler_sig_int_fail.49528482692973625675281103879347370028415875560864793141856456133751998001472
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 149822534 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.classb_state
  UVM_INFO @ 149822534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:741) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 33.alert_handler_stress_all_with_rand_reset.97877171964097919981553465739783407722655009777588229920057051361439564255116
    Line 68073, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55362739141 ps: (cip_base_vseq.sv:741) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 55362739141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:491) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 43.alert_handler_sig_int_fail.23431668652609400717198173258146130579880507058331256671381360025276513322731
    Line 583, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 824762098 ps: (cip_base_vseq.sv:491) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 824762098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 44.alert_handler_sig_int_fail.11025515080018939543406690325655633535419489935477950366046467058962783510087
    Line 829, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 775453783 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 775453783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 48.alert_handler_stress_all_with_rand_reset.14112689563089724828510129164605028462633034784110102592876415870237405029345
    Line 105536, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28290887630 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 28290887630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0cdf265eaa`