ALERT_HANDLER Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.220m	7.029ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.920s	109.575us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.080s	1.071ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.311m	28.466ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.926m	3.417ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.240s	188.602us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.080s	1.071ms	20	20	100.00
		alert_handler_csr_aliasing	3.926m	3.417ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.113m	30.790ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.401m	19.713ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.605m	57.390ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.252m	1.164ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.220m	7.029ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.527m	2.370ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.337m	9.448ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.893m	56.733ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.357m	831.457ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.566m	133.794ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.198h	69.210ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.140m	1.651ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.190s	44.155us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.730s	14.593us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	30.730s	2.892ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	30.730s	2.892ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.920s	109.575us	5	5	100.00
		alert_handler_csr_rw	9.080s	1.071ms	20	20	100.00
		alert_handler_csr_aliasing	3.926m	3.417ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.270s	13.473ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.920s	109.575us	5	5	100.00
		alert_handler_csr_rw	9.080s	1.071ms	20	20	100.00
		alert_handler_csr_aliasing	3.926m	3.417ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.270s	13.473ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.886m	48.313ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.886m	48.313ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.886m	48.313ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.886m	48.313ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.529m	17.616ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
		alert_handler_tl_intg_err	1.385m	2.533ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.385m	2.533ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.886m	48.313ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.220m	7.029ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.220m	7.029ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.220m	7.029ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.220m	7.029ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.252m	1.164ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.357m	831.457ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.252m	1.164ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.605m	57.390ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.605m	57.390ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	57.330s	2.666ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.344h	305.315ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.72	99.97	100.00	100.00	99.38	99.48

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 1.alert_handler_stress_all_with_rand_reset.28047129230220418813404075304631457291540575584624908888247882336169724267722
      Line 6432, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55615918403 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 55615918403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.49490281492627523318431647769049366119210220584380358828842726599382095833566
      Line 16970, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67142216976 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 67142216976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 3.alert_handler_stress_all_with_rand_reset.75289368496593698553408281269163175895805102940868884239105229967319986594266
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:56d96894-784b-4ccc-b9f3-c5ba1814cba0
      

    • 14.alert_handler_stress_all_with_rand_reset.15475467389086285791491934293547815842788772512200206548913094209645441292059
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:2eac5103-41f3-47ac-8238-f81ee0109141
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 4.alert_handler_stress_all_with_rand_reset.111045051114587648075893313147231430021275763809379791642656688292320282819746
      Line 10154, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10475693773 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 10475693773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.04_05.18.56
• 2024.03.01_08.17.29
• 2024.02.26_04.00.47
• 2024.02.22_05.14.32
• 2024.02.19_06.17.59
• 2024.02.14_22.11.46