ALERT_HANDLER Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	56.800s	1.753ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.510s	142.144us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.550s	323.644us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	3.015m	18.134ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.782m	4.596ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.740s	365.486us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.550s	323.644us	20	20	100.00
		alert_handler_csr_aliasing	4.782m	4.596ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.040m	12.351ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.253m	5.237ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.529m	65.775ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.193m	3.650ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	56.800s	1.753ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.349m	5.392ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.238m	5.052ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.925m	17.426ms	50	50	100.00
V2	lpg	alert_handler_lpg	49.682m	192.054ms	50	50	100.00
		alert_handler_lpg_stub_clk	59.075m	161.440ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.177h	286.059ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	53.740s	1.223ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.050s	172.456us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.730s	44.325us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.010s	264.804us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.010s	264.804us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.510s	142.144us	5	5	100.00
		alert_handler_csr_rw	9.550s	323.644us	20	20	100.00
		alert_handler_csr_aliasing	4.782m	4.596ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.190s	2.719ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.510s	142.144us	5	5	100.00
		alert_handler_csr_rw	9.550s	323.644us	20	20	100.00
		alert_handler_csr_aliasing	4.782m	4.596ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.190s	2.719ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.264m	5.437ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.264m	5.437ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.264m	5.437ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.264m	5.437ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.611m	17.516ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
		alert_handler_tl_intg_err	1.481m	12.397ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.481m	12.397ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.264m	5.437ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	56.800s	1.753ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	56.800s	1.753ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	56.800s	1.753ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	56.800s	1.753ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.193m	3.650ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	49.682m	192.054ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.193m	3.650ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.529m	65.775ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.529m	65.775ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.710s	808.382us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.697h	820.873ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			824	850	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.49	99.99	98.71	92.05	100.00	100.00	99.30	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test alert_handler_stress_all_with_rand_reset has 23 failures.

    • 1.alert_handler_stress_all_with_rand_reset.110744413467390930124151431291867931007049379123152984996157216035376469865001
      Line 9076, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26079675422 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26079675422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.7254218583977832524246934048431024050256524433230188472458289728450099179123
      Line 66976, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 782154510449 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 782154510449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 19.alert_handler_stress_all_with_rand_reset.70803776235522564763684234937077298035327650077040313073571621945931204042887
      Line 69803, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17767766952 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 17767766952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 32.alert_handler_stress_all_with_rand_reset.60809896058425565752733603289781605985731385597705214195128317955160118831307
      Line 3386, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2351068222 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 2351068222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 43.alert_handler_stress_all_with_rand_reset.114212771349959309504383681600479994253265164825614827922688172026290996201030
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:11248d55-d50e-4fbf-a197-bda5c3527ac3
      

Past Results

• Latest
• lint
• 2024.03.06_08.32.44
• 2024.03.04_05.18.56
• 2024.03.01_08.17.29
• 2024.02.26_04.00.47
• 2024.02.22_05.14.32
• 2024.02.19_06.17.59