ALERT_HANDLER Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.234m	1.233ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.040s	870.399us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.650s	128.792us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.357m	8.921ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.648m	2.267ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.320s	412.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.650s	128.792us	20	20	100.00
		alert_handler_csr_aliasing	2.648m	2.267ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.337m	5.558ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.121m	2.245ms	50	50	100.00
V2	entropy	alert_handler_entropy	50.819m	53.235ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.014m	9.070ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.234m	1.233ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.214m	2.332ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.029m	1.020ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.057m	32.996ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.829m	169.341ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.800m	645.407ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.236h	97.775ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.268m	1.880ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.320s	52.911us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.880s	17.536us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	20.400s	568.155us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	20.400s	568.155us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.040s	870.399us	5	5	100.00
		alert_handler_csr_rw	10.650s	128.792us	20	20	100.00
		alert_handler_csr_aliasing	2.648m	2.267ms	5	5	100.00
		alert_handler_same_csr_outstanding	57.890s	1.389ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.040s	870.399us	5	5	100.00
		alert_handler_csr_rw	10.650s	128.792us	20	20	100.00
		alert_handler_csr_aliasing	2.648m	2.267ms	5	5	100.00
		alert_handler_same_csr_outstanding	57.890s	1.389ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.361m	8.408ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.361m	8.408ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.361m	8.408ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.361m	8.408ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.966m	65.331ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
		alert_handler_tl_intg_err	1.444m	2.375ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.444m	2.375ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.361m	8.408ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.234m	1.233ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.234m	1.233ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.234m	1.233ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.234m	1.233ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.014m	9.070ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.829m	169.341ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.014m	9.070ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	50.819m	53.235ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	50.819m	53.235ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	49.690s	1.128ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.753h	375.744ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.99	98.70	91.98	100.00	100.00	99.38	99.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test alert_handler_stress_all_with_rand_reset has 16 failures.
  - 0.alert_handler_stress_all_with_rand_reset.5897733797270877569369551287003381892586108142960540894344592218565137193743
    Line 4581, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16044089813 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16044089813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.58128334625589258340106347758098951076338790343453603851677561301950713624082
    Line 11871, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14474223034 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14474223034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 27.alert_handler_stress_all_with_rand_reset.94536695821594413846177029599674424650456137361522203394307431277508943711767
    Line 66715, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44778455859 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 44778455859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 31.alert_handler_stress_all_with_rand_reset.77238236620372635947938518816777213676419957380812804157675724708906437746566
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3180e4f7-119f-473d-aaa8-aca3f36fb6aa
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 39.alert_handler_stress_all_with_rand_reset.85060566156237975525500106113348164220436805530387400132735792015889715532162
    Line 193730, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 78248672016 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (826 [0x33a] vs 950 [0x3b6])
  UVM_INFO @ 78248672016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 49.alert_handler_sig_int_fail.11036089676711706252927671057825553754030150100032929881635174550325046656623
    Line 746, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 310358897 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 310358897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8d1fda3660`