ALERT_HANDLER Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.246m	4.914ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.720s	535.054us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.100s	954.512us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.237m	7.710ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.147m	3.258ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.760s	960.271us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.100s	954.512us	20	20	100.00
		alert_handler_csr_aliasing	4.147m	3.258ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.712m	5.430ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.201m	2.503ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.176m	787.189ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.164m	1.028ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.246m	4.914ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.372m	1.220ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.355m	4.967ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.514m	94.186ms	49	50	98.00
V2	lpg	alert_handler_lpg	56.610m	51.581ms	48	50	96.00
		alert_handler_lpg_stub_clk	53.242m	108.578ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	57.980m	235.487ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.177m	1.686ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.480s	79.487us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.890s	16.547us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	23.100s	350.197us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	23.100s	350.197us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.720s	535.054us	5	5	100.00
		alert_handler_csr_rw	10.100s	954.512us	20	20	100.00
		alert_handler_csr_aliasing	4.147m	3.258ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.580s	1.778ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.720s	535.054us	5	5	100.00
		alert_handler_csr_rw	10.100s	954.512us	20	20	100.00
		alert_handler_csr_aliasing	4.147m	3.258ms	5	5	100.00
		alert_handler_same_csr_outstanding	42.580s	1.778ms	20	20	100.00
V2		TOTAL			624	630	99.05
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.396m	34.351ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.396m	34.351ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.396m	34.351ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.396m	34.351ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.974m	67.441ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
		alert_handler_tl_intg_err	1.191m	3.720ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.191m	3.720ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.396m	34.351ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.246m	4.914ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.246m	4.914ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.246m	4.914ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.246m	4.914ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.164m	1.028ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.610m	51.581ms	48	50	96.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.164m	1.028ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.176m	787.189ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.176m	787.189ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	32.640s	668.632us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.530h	480.051ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			828	850	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	11	73.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.72	99.97	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test alert_handler_stress_all_with_rand_reset has 13 failures.
  - 1.alert_handler_stress_all_with_rand_reset.89396311378101967293214902007235893455417735814428599364336048816154639918147
    Line 33083, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29529467269 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29529467269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.22281814852007422707405088422275901048776956898024906109998747346268208162725
    Line 7708, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22302889635 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22302889635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test alert_handler_stress_all_with_rand_reset has 3 failures.
  - 3.alert_handler_stress_all_with_rand_reset.106875152133674917073688591929262498789012925148294394004968787784511947887150
    Line 13510, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50669760159 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 50669760159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.alert_handler_stress_all_with_rand_reset.40330724228154552953317851493662179479622353405132630653058493958310930244723
    Line 114789, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55000612598 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 55000612598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_lpg has 2 failures.
  - 27.alert_handler_lpg.30100135873474960667753114538593921011888556636654570635366049358043986243582
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_lpg/latest/run.log
```
  Job ID: smart:c4f52213-3425-487f-8d5d-67da84dbe096
```
  - 41.alert_handler_lpg.54390915678228234879653514901461831911150060205891636526681475722407403942136
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_lpg/latest/run.log
```
  Job ID: smart:3b12f526-78cd-49d5-aa3d-c68214a1deab
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 14.alert_handler_stress_all.60635306999553364668453891225736918026011780370224806311452021054019675360690
    Line 60691, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 43709312975 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 6 [0x6]) reg name: alert_handler_reg_block.classc_state
  UVM_INFO @ 43709312975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 15.alert_handler_sig_int_fail.87064290680908886662366514294210669097141645169452479874629284967709638744381
    Line 581, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 244780438 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 244780438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 16.alert_handler_sig_int_fail.66672227028642399220575931677203369903632010129610631988146614402656420103888
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 105750679 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 105750679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscPingFail has 1 failures:
- Test alert_handler_ping_timeout has 1 failures.
  - 48.alert_handler_ping_timeout.9314814152569628074970766099162929132742169732537331914680186770060771513303
    Line 350, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest/run.log
```
  UVM_ERROR @ 690193583 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscPingFail
  UVM_INFO @ 690193583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `bc285b7382`