ALERT_HANDLER Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.282m	6.928ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.960s	476.368us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.970s	558.975us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.801m	4.265ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.543m	18.351ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.660s	1.581ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.970s	558.975us	20	20	100.00
		alert_handler_csr_aliasing	5.543m	18.351ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.341m	21.329ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.293m	5.290ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.404m	57.526ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.302m	2.287ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.282m	6.928ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.364m	24.008ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.470m	2.291ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.127m	29.499ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.509m	124.526ms	50	50	100.00
		alert_handler_lpg_stub_clk	49.114m	50.719ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.016h	132.338ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	49.950s	1.223ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.500s	190.506us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.800s	10.453us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	30.770s	1.531ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	30.770s	1.531ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.960s	476.368us	5	5	100.00
		alert_handler_csr_rw	9.970s	558.975us	20	20	100.00
		alert_handler_csr_aliasing	5.543m	18.351ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.260s	2.800ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.960s	476.368us	5	5	100.00
		alert_handler_csr_rw	9.970s	558.975us	20	20	100.00
		alert_handler_csr_aliasing	5.543m	18.351ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.260s	2.800ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.086m	5.653ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.086m	5.653ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.086m	5.653ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.086m	5.653ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.792m	16.897ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
		alert_handler_tl_intg_err	1.481m	2.600ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.481m	2.600ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.086m	5.653ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.282m	6.928ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.282m	6.928ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.282m	6.928ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.282m	6.928ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.302m	2.287ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.509m	124.526ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.302m	2.287ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.404m	57.526ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.404m	57.526ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	29.690s	927.062us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.484h	118.041ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.74	100.00	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 0.alert_handler_stress_all_with_rand_reset.94522651140793626743973760864792188753826552874068587456920166010010398069247
      Line 12296, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48443735583 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 48443735583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.109306543283317841958561578929872538215646998940806196543669677835936128674410
      Line 11046, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20141397899 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20141397899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 28.alert_handler_stress_all_with_rand_reset.23081291813007396460755459300390886358356395287673729136347714623670953241679
      Line 69506, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 135506648697 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 6 [0x6]) reg name: alert_handler_reg_block.classa_state
        UVM_INFO @ 135506648697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 46.alert_handler_stress_all_with_rand_reset.23645620510383746433155842023995777510545739214513867052348014541464399309080
      Line 70149, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17312451674 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 17312451674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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