ALERT_HANDLER Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.361m	4.467ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	12.270s	1.722ms	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.000s	401.997us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.129m	5.702ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.757m	12.334ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.770s	558.252us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.000s	401.997us	20	20	100.00
		alert_handler_csr_aliasing	5.757m	12.334ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.356m	58.817ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.189m	5.027ms	50	50	100.00
V2	entropy	alert_handler_entropy	52.028m	113.285ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.074m	3.573ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.361m	4.467ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.295m	2.260ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.302m	4.658ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.288m	57.266ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.496m	243.012ms	49	50	98.00
		alert_handler_lpg_stub_clk	56.517m	929.844ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.391h	460.593ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.029m	3.721ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.520s	165.684us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.060s	20.762us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	23.400s	739.079us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	23.400s	739.079us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	12.270s	1.722ms	5	5	100.00
		alert_handler_csr_rw	11.000s	401.997us	20	20	100.00
		alert_handler_csr_aliasing	5.757m	12.334ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.470s	676.590us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	12.270s	1.722ms	5	5	100.00
		alert_handler_csr_rw	11.000s	401.997us	20	20	100.00
		alert_handler_csr_aliasing	5.757m	12.334ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.470s	676.590us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.609m	21.923ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.609m	21.923ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.609m	21.923ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.609m	21.923ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.096m	65.835ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
		alert_handler_tl_intg_err	1.426m	1.388ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.426m	1.388ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.609m	21.923ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.361m	4.467ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.361m	4.467ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.361m	4.467ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.361m	4.467ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.074m	3.573ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.496m	243.012ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.074m	3.573ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	52.028m	113.285ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	52.028m	113.285ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	28.130s	890.464us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.394h	167.371ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.72	100.00	100.00	100.00	99.38	99.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test alert_handler_stress_all_with_rand_reset has 18 failures.
  - 0.alert_handler_stress_all_with_rand_reset.20438821534505186122835169260957744042263146430932801350969757920906061181688
    Line 591, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 360062854 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 360062854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.alert_handler_stress_all_with_rand_reset.112684000944380874944565688771659502971494223752119166339448374648875880581949
    Line 12599, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8890788957 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8890788957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_lpg has 1 failures.
  - 0.alert_handler_lpg.99370738386172045409359847129396332263105363234684782182636281308811606348719
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_lpg/latest/run.log
```
  Job ID: smart:1559cfdd-36c0-4125-bf96-afd67412e489
```
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 8.alert_handler_lpg_stub_clk.38070034957469015744882957826824675934687129636876071482760590964269981245206
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest/run.log
```
  Job ID: smart:6464e8f3-c33b-4427-b4d5-32b7fe3e0604
```
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 8.alert_handler_stress_all_with_rand_reset.99853025599072913245469722898549447627759388593682201607133161361202366536719
    Line 10335, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23685834929 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 23685834929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 42.alert_handler_sig_int_fail.75042443405795506986693322996039664371318293202305301834407186496818651561977
    Line 582, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 190102151 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 3 [0x3]) reg name: alert_handler_reg_block.classd_state
  UVM_INFO @ 190102151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 46.alert_handler_stress_all_with_rand_reset.4867906028901319854792139966141405117523460434829395356824760151618830093730
    Line 34035, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61595442279 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 61595442279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c187a82ee8`