ALERT_HANDLER Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.183m	1.978ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.590s	142.631us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.850s	105.281us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.078m	7.575ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.694m	4.374ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.560s	1.007ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.850s	105.281us	20	20	100.00
		alert_handler_csr_aliasing	4.694m	4.374ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.613m	6.267ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.396m	2.738ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.203m	224.537ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.232m	3.900ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.183m	1.978ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.061m	1.813ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.189m	4.188ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.238m	79.134ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.062m	231.817ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.969m	54.658ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.294h	327.993ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.184m	16.879ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.270s	167.352us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.840s	19.310us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.450s	344.555us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.450s	344.555us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.590s	142.631us	5	5	100.00
		alert_handler_csr_rw	9.850s	105.281us	20	20	100.00
		alert_handler_csr_aliasing	4.694m	4.374ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.340s	2.727ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.590s	142.631us	5	5	100.00
		alert_handler_csr_rw	9.850s	105.281us	20	20	100.00
		alert_handler_csr_aliasing	4.694m	4.374ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.340s	2.727ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.219m	63.935ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.219m	63.935ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.219m	63.935ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.219m	63.935ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.297m	279.117ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
		alert_handler_tl_intg_err	1.259m	9.822ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.259m	9.822ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.219m	63.935ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.183m	1.978ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.183m	1.978ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.183m	1.978ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.183m	1.978ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.232m	3.900ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.062m	231.817ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.232m	3.900ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.203m	224.537ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.203m	224.537ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.110s	484.156us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.585h	179.376ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.76	99.97	100.00	100.00	99.38	99.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test alert_handler_stress_all_with_rand_reset has 16 failures.

    • 4.alert_handler_stress_all_with_rand_reset.1963852566633809408214331937091375575433499646484313784076560324674288105766
      Line 9425, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 144859004172 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 144859004172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.alert_handler_stress_all_with_rand_reset.77141694452299199961165901695342563027875549909834167777677503712197981924521
      Line 15422, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32573513671 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32573513671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 29.alert_handler_stress_all_with_rand_reset.92943021545629777654920681448968787756245582180753762415915880166558845287061
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:34f00ad9-b233-4555-aa03-e4d8d422f518
      

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 33.alert_handler_lpg_stub_clk.53807096582606706415986527605197081254940513585542447605363959102959442345831
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:d6bdb2ac-7253-4b6c-b022-d07dcfe8faf0
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 37.alert_handler_stress_all_with_rand_reset.95628737575027520393278274743777179430466465360423601711727552239069777674270
      Line 113759, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 341736175220 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 3 [0x3]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 341736175220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.18_04.54.57
• 2024.03.15_00.27.51
• 2024.03.13_04.23.55
• 2024.03.11_03.42.26
• 2024.03.08_05.29.19
• 2024.03.06_08.32.44