ALERT_HANDLER Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.660s	100.512us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.650s	126.760us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.285m	35.547ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.458m	7.557ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.750s	242.994us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.650s	126.760us	20	20	100.00
		alert_handler_csr_aliasing	5.458m	7.557ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.660m	110.463ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.262m	4.802ms	50	50	100.00
V2	entropy	alert_handler_entropy	50.855m	46.861ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.073m	1.056ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.170m	7.495ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.198m	2.771ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.026m	14.728ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.509m	60.465ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.478m	54.286ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.215h	299.572ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.179m	14.812ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.820s	50.595us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.810s	20.336us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.890s	325.049us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.890s	325.049us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.660s	100.512us	5	5	100.00
		alert_handler_csr_rw	9.650s	126.760us	20	20	100.00
		alert_handler_csr_aliasing	5.458m	7.557ms	5	5	100.00
		alert_handler_same_csr_outstanding	57.940s	1.780ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.660s	100.512us	5	5	100.00
		alert_handler_csr_rw	9.650s	126.760us	20	20	100.00
		alert_handler_csr_aliasing	5.458m	7.557ms	5	5	100.00
		alert_handler_same_csr_outstanding	57.940s	1.780ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.698m	4.580ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.698m	4.580ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.698m	4.580ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.698m	4.580ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.181m	63.893ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
		alert_handler_tl_intg_err	1.338m	8.765ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.338m	8.765ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.698m	4.580ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.073m	1.056ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.509m	60.465ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.073m	1.056ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	50.855m	46.861ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	50.855m	46.861ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	53.160s	1.229ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.953h	138.470ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.69	99.97	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test alert_handler_stress_all_with_rand_reset has 20 failures.

    • 0.alert_handler_stress_all_with_rand_reset.77086705513209447886631507364948917544844681916000545184951385977354914660994
      Line 42158, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42989177611 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 42989177611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.99932723985883451263360009732978953571026396167387873006989551381944104759369
      Line 8785, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40123779279 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 40123779279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 29.alert_handler_lpg_stub_clk.56044414788152452725317159185841179716765923447647780158517911480324782413939
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:4d4b0796-b943-4e92-b8ab-8196f72d912b
      

  • Test alert_handler_entropy has 1 failures.

    • 31.alert_handler_entropy.95402548740369289215031503334565714625432228768160067745220085457170633165233
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_entropy/latest/run.log

        Job ID: smart:76b8b96e-8ac1-4243-b713-1e90d3e61757
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 48.alert_handler_stress_all_with_rand_reset.57648687289535730790249602273786432143153546995185479923988342088045524977094
      Line 6648, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9652754007 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 9652754007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.03.20_03.57.45
• 2024.03.18_04.54.57
• 2024.03.15_00.27.51
• 2024.03.13_04.23.55
• 2024.03.11_03.42.26
• 2024.03.08_05.29.19