70ad420931| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.285m | 5.037ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 11.240s | 362.734us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 9.480s | 1.026ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.531m | 8.557ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 2.254m | 2.775ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 15.100s | 217.789us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 9.480s | 1.026ms | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 2.254m | 2.775ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.789m | 31.216ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.162m | 4.822ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 51.335m | 205.788ms | 48 | 50 | 96.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.117m | 1.605ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.285m | 5.037ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.368m | 6.332ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.133m | 5.110ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.796m | 73.864ms | 49 | 50 | 98.00 |
| V2 | lpg | alert_handler_lpg | 57.289m | 189.083ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 56.633m | 61.945ms | 47 | 50 | 94.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.228h | 68.365ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.001m | 5.637ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 5.300s | 61.968us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.870s | 19.014us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 26.050s | 1.498ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 26.050s | 1.498ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 11.240s | 362.734us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.480s | 1.026ms | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 2.254m | 2.775ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 52.530s | 2.722ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 11.240s | 362.734us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.480s | 1.026ms | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 2.254m | 2.775ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 52.530s | 2.722ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 622 | 630 | 98.73 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 5.926m | 6.413ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 5.926m | 6.413ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 5.926m | 6.413ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 5.926m | 6.413ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 19.594m | 19.465ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.388m | 5.156ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.388m | 5.156ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 5.926m | 6.413ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.285m | 5.037ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.285m | 5.037ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.285m | 5.037ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.285m | 5.037ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.117m | 1.605ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 57.289m | 189.083ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.117m | 1.605ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 51.335m | 205.788ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 51.335m | 205.788ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 3.451m | 5.319ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.507h | 168.763ms | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 827 | 850 | 97.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 10 | 66.67 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.65 | 99.99 | 98.68 | 100.00 | 100.00 | 100.00 | 99.38 | 99.48 |
UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
2.alert_handler_stress_all_with_rand_reset.5300394862638159608229931981283170405935989473855718104607750580946293158285
Line 7388, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6993445136 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6993445136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.alert_handler_stress_all_with_rand_reset.100799361238529268162505813034606711338933919719626702553961326355544636268374
Line 30827, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45693602329 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 45693602329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
6.alert_handler_lpg_stub_clk.19294567574788870779642523828045473604844529057040626157291278993336275483469
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:647a0ff8-898b-4b49-a582-7cc406c0b56e
9.alert_handler_lpg_stub_clk.89525322861218890083410756127836816981169778025126627090335134810305481878785
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:1ed3d255-09b9-43a8-ac30-c1b6dd5f7033
... and 1 more failures.
24.alert_handler_entropy.36307578549358188429865847963041800799248237043323147371484669903175262918560
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_entropy/latest/run.log
Job ID: smart:7fb42070-9ad0-4c27-9fbd-46ed6f3a848d
37.alert_handler_entropy.56065406470966999307941213044817923133650751447078418327688374921449325956203
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_entropy/latest/run.log
Job ID: smart:244175bf-4fbc-4f51-9698-a1227458cf75
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
Test alert_handler_stress_all has 1 failures.
8.alert_handler_stress_all.50249707418527283662441817753437814347871823963606950285985324803000836393861
Line 749, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 305550215 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 305550215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test alert_handler_stress_all_with_rand_reset has 1 failures.
20.alert_handler_stress_all_with_rand_reset.111331678244239005541919571901274273613203130514007675117261436217527395775445
Line 23317, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52987206995 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 52987206995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
31.alert_handler_stress_all_with_rand_reset.62972904595905469896596231907657195463604833226747788911815758759876257868058
Line 62846, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 94376034255 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 94376034255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.alert_handler_stress_all_with_rand_reset.53580844354427361170626399144772220735926012923638126041009433161451395484696
Line 30014, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15596041753 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 15596041753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:330) [scoreboard] Check failed cycle_cnt <= exp_cycle (* [*] vs * [*]) has 1 failures:
34.alert_handler_ping_timeout.67381677463252506441349192377522021680214722655731207538383873347987735809731
Line 339, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest/run.log
UVM_ERROR @ 1402850766 ps: (alert_handler_scoreboard.sv:330) [uvm_test_top.env.scoreboard] Check failed cycle_cnt <= exp_cycle (561 [0x231] vs 59 [0x3b])
UVM_INFO @ 1402850766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
46.alert_handler_sig_int_fail.19091359681147262181879794589839145669099129985125337088956634658040567839187
Line 581, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 748301626 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 748301626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---