ALERT_HANDLER Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.179m	1.103ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.310s	420.956us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.410s	131.223us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.235m	9.167ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	6.219m	18.088ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.730s	162.077us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.410s	131.223us	20	20	100.00
		alert_handler_csr_aliasing	6.219m	18.088ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.963m	15.975ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.221m	5.567ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.564m	57.570ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.227m	2.169ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.179m	1.103ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.394m	1.202ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.338m	2.342ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.147m	26.610ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.226m	289.350ms	50	50	100.00
		alert_handler_lpg_stub_clk	57.424m	141.808ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.097h	289.395ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.278m	3.458ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.920s	243.502us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.820s	15.409us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	29.800s	1.478ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	29.800s	1.478ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.310s	420.956us	5	5	100.00
		alert_handler_csr_rw	9.410s	131.223us	20	20	100.00
		alert_handler_csr_aliasing	6.219m	18.088ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.040s	999.015us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.310s	420.956us	5	5	100.00
		alert_handler_csr_rw	9.410s	131.223us	20	20	100.00
		alert_handler_csr_aliasing	6.219m	18.088ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.040s	999.015us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.458m	5.946ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.458m	5.946ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.458m	5.946ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.458m	5.946ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.526m	69.469ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
		alert_handler_tl_intg_err	1.221m	1.147ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.221m	1.147ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.458m	5.946ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.179m	1.103ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.179m	1.103ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.179m	1.103ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.179m	1.103ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.227m	2.169ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.226m	289.350ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.227m	2.169ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.564m	57.570ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.564m	57.570ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.350s	4.105ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.945h	929.811ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.65	100.00	100.00	100.00	99.38	99.76

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 1.alert_handler_stress_all_with_rand_reset.81511121220969015333121948508087141701046368967995745921210890696688537292425
      Line 34321, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32915202178 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32915202178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.112383820108721754269046510251792093702437131681473958811466405711547505209221
      Line 41163, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32480705427 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32480705427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 21.alert_handler_stress_all_with_rand_reset.74012574159327341057561693247780037301816179213790741255140590525429158069735
      Line 109892, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 143511466243 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 143511466243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 40.alert_handler_sig_int_fail.37681284786116377806163458798943564888851702042839720067574896028315645583511
      Line 417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 136943784 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (210 [0xd2] vs 211 [0xd3]) reg name: alert_handler_reg_block.classa_accum_cnt
        UVM_INFO @ 136943784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 45.alert_handler_stress_all.23690171986726190194212636127866896670007780655309120226360825095163805270728
      Line 53260, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 120309585430 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 120309585430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 46.alert_handler_sig_int_fail.54398975895456695874755440791223786052742750697942483296428383443838705404023
      Line 581, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 1296866842 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 7 [0x7]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @ 1296866842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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