ALERT_HANDLER Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.301m	1.329ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.990s	480.220us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.160s	1.254ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.501m	22.886ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.138m	4.067ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.070s	1.288ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.160s	1.254ms	20	20	100.00
		alert_handler_csr_aliasing	4.138m	4.067ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.713m	5.950ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.114m	871.448us	50	50	100.00
V2	entropy	alert_handler_entropy	54.252m	53.989ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.069m	980.925us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.301m	1.329ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	55.820s	2.048ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.063m	5.099ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.511m	76.637ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.339m	119.988ms	50	50	100.00
		alert_handler_lpg_stub_clk	44.140m	73.979ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.362h	122.863ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.552m	2.266ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.540s	54.061us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.930s	21.688us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	17.000s	309.989us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	17.000s	309.989us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.990s	480.220us	5	5	100.00
		alert_handler_csr_rw	10.160s	1.254ms	20	20	100.00
		alert_handler_csr_aliasing	4.138m	4.067ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.640s	713.692us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.990s	480.220us	5	5	100.00
		alert_handler_csr_rw	10.160s	1.254ms	20	20	100.00
		alert_handler_csr_aliasing	4.138m	4.067ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.640s	713.692us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.758m	11.918ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.758m	11.918ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.758m	11.918ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.758m	11.918ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.080m	64.379ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
		alert_handler_tl_intg_err	1.442m	2.519ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.442m	2.519ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.758m	11.918ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.301m	1.329ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.301m	1.329ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.301m	1.329ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.301m	1.329ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.069m	980.925us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.339m	119.988ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.069m	980.925us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.252m	53.989ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.252m	53.989ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	25.020s	948.883us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.392h	78.854ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			826	850	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.66	100.00	100.00	100.00	99.38	99.48

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test alert_handler_stress_all_with_rand_reset has 20 failures.

    • 2.alert_handler_stress_all_with_rand_reset.96989953692856534013512033011013875876545706809846403192994320832346735861428
      Line 18984, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67860055206 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 67860055206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.2531141090263485474756626322997622295561556153025200515834675781426498907400
      Line 6462, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12189925672 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12189925672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 2 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 31.alert_handler_stress_all.6653893145149771922223965914610349171421715914022895499197951007022851405185
      Line 46804, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 87846435892 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 87846435892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 45.alert_handler_stress_all_with_rand_reset.100923258504614347559829364214304147770090079232330360053542371841849895679294
      Line 3477, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13395829165 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 13395829165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 38.alert_handler_stress_all_with_rand_reset.66666892146402943361791516354651801735933216558508254482766374598802274339530
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d71865f8-74f7-4aa5-b72d-d99cd71adce0
      

    • 44.alert_handler_stress_all_with_rand_reset.37399790002778211087109894992458597412513475326609732215724091526765404994835
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d917da27-5efe-46c1-8188-ef2e3ca404dd
      

Past Results

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