ALERT_HANDLER Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.075m	1.380ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.740s	195.466us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.900s	127.977us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	3.985m	4.446ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.898m	54.228ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.000s	266.531us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.900s	127.977us	20	20	100.00
		alert_handler_csr_aliasing	4.898m	54.228ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.223m	8.449ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	58.930s	3.853ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.248m	52.182ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.197m	2.294ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.075m	1.380ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.115m	1.795ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.187m	3.934ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.003m	15.013ms	50	50	100.00
V2	lpg	alert_handler_lpg	51.895m	213.452ms	50	50	100.00
		alert_handler_lpg_stub_clk	59.140m	215.925ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.239h	161.982ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	48.780s	1.204ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.000s	55.617us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.520s	33.041us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	23.400s	622.333us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	23.400s	622.333us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.740s	195.466us	5	5	100.00
		alert_handler_csr_rw	8.900s	127.977us	20	20	100.00
		alert_handler_csr_aliasing	4.898m	54.228ms	5	5	100.00
		alert_handler_same_csr_outstanding	40.970s	701.542us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.740s	195.466us	5	5	100.00
		alert_handler_csr_rw	8.900s	127.977us	20	20	100.00
		alert_handler_csr_aliasing	4.898m	54.228ms	5	5	100.00
		alert_handler_same_csr_outstanding	40.970s	701.542us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.199m	10.746ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.199m	10.746ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.199m	10.746ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.199m	10.746ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	17.217m	15.348ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
		alert_handler_tl_intg_err	1.169m	4.131ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.169m	4.131ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.199m	10.746ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.075m	1.380ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.075m	1.380ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.075m	1.380ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.075m	1.380ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.197m	2.294ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	51.895m	213.452ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.197m	2.294ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.248m	52.182ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.248m	52.182ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.840s	435.292us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.928h	535.241ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.71	100.00	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 1.alert_handler_stress_all_with_rand_reset.107987996964219680487579069035331398547372015510010678698287084526045595801418
      Line 35909, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 105838762908 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 105838762908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.13633888856441404078980413334237969020748450195410726365733723621931637176252
      Line 12523, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45147022544 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 45147022544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 7.alert_handler_stress_all_with_rand_reset.35607837830821992116913931985701380150507008469130852260397492575443756678688
      Line 22698, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 83875131609 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 83875131609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:330) [scoreboard] Check failed cycle_cnt <= exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 35.alert_handler_sig_int_fail.29883771763910936726968467281950052106930045398651065228550205234949003240032
      Line 665, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 477011803 ps: (alert_handler_scoreboard.sv:330) [uvm_test_top.env.scoreboard] Check failed cycle_cnt <= exp_cycle (263 [0x107] vs 228 [0xe4])
        UVM_INFO @ 477011803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.29_04.28.58
• 2024.03.27_04.57.27
• 2024.03.25_04.20.45
• 2024.03.22_04.58.22
• 2024.03.20_03.57.45
• 2024.03.18_04.54.57