ALERT_HANDLER Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.192m 3.916ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 6.790s 145.875us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 10.120s 132.436us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 4.331m 4.364ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 4.246m 3.459ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 12.430s 148.416us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 10.120s 132.436us 20 20 100.00
alert_handler_csr_aliasing 4.246m 3.459ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 5.339m 5.912ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.356m 2.538ms 50 50 100.00
V2 entropy alert_handler_entropy 53.254m 95.630ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.181m 15.057ms 49 50 98.00
V2 clk_skew alert_handler_smoke 1.192m 3.916ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.103m 1.128ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.151m 2.222ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 9.977m 30.294ms 50 50 100.00
V2 lpg alert_handler_lpg 49.430m 439.217ms 50 50 100.00
alert_handler_lpg_stub_clk 48.139m 207.450ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.146h 69.282ms 50 50 100.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 1.805m 21.356ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.190s 176.949us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.790s 14.832us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 19.860s 1.081ms 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 19.860s 1.081ms 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 6.790s 145.875us 5 5 100.00
alert_handler_csr_rw 10.120s 132.436us 20 20 100.00
alert_handler_csr_aliasing 4.246m 3.459ms 5 5 100.00
alert_handler_same_csr_outstanding 57.790s 11.756ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 6.790s 145.875us 5 5 100.00
alert_handler_csr_rw 10.120s 132.436us 20 20 100.00
alert_handler_csr_aliasing 4.246m 3.459ms 5 5 100.00
alert_handler_same_csr_outstanding 57.790s 11.756ms 20 20 100.00
V2 TOTAL 629 630 99.84
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 6.696m 30.218ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 6.696m 30.218ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 6.696m 30.218ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 6.696m 30.218ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 21.226m 84.287ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
alert_handler_tl_intg_err 1.434m 8.259ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.434m 8.259ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 6.696m 30.218ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.192m 3.916ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.192m 3.916ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.192m 3.916ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.192m 3.916ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.181m 15.057ms 49 50 98.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 49.430m 439.217ms 50 50 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.181m 15.057ms 49 50 98.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 53.254m 95.630ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 53.254m 95.630ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 40.010s 960.172us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.130h 96.262ms 33 50 66.00
V3 TOTAL 33 50 66.00
TOTAL 832 850 97.88

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 14 93.33
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.66 99.99 98.68 99.97 100.00 100.00 99.38 99.60

Failure Buckets

Past Results