ALERT_HANDLER Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.233m	9.978ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.250s	56.709us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.230s	507.883us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.176m	13.604ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.775m	4.731ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	17.410s	805.673us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.230s	507.883us	20	20	100.00
		alert_handler_csr_aliasing	2.775m	4.731ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.133m	46.934ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.325m	2.471ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.560m	338.583ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.096m	3.461ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.233m	9.978ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.333m	8.146ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.351m	3.024ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.180m	59.791ms	50	50	100.00
V2	lpg	alert_handler_lpg	51.103m	190.194ms	50	50	100.00
		alert_handler_lpg_stub_clk	59.729m	56.376ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.335h	84.673ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	48.220s	2.136ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.260s	44.849us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.860s	71.522us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	29.870s	431.443us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	29.870s	431.443us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.250s	56.709us	5	5	100.00
		alert_handler_csr_rw	10.230s	507.883us	20	20	100.00
		alert_handler_csr_aliasing	2.775m	4.731ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.930s	711.526us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.250s	56.709us	5	5	100.00
		alert_handler_csr_rw	10.230s	507.883us	20	20	100.00
		alert_handler_csr_aliasing	2.775m	4.731ms	5	5	100.00
		alert_handler_same_csr_outstanding	55.930s	711.526us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.920m	4.618ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.920m	4.618ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.920m	4.618ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.920m	4.618ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.780m	68.312ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
		alert_handler_tl_intg_err	1.481m	1.240ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.481m	1.240ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.920m	4.618ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.233m	9.978ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.233m	9.978ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.233m	9.978ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.233m	9.978ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.096m	3.461ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	51.103m	190.194ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.096m	3.461ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.560m	338.583ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.560m	338.583ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	53.880s	1.254ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.895h	221.469ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			833	850	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.99	98.74	100.00	100.00	100.00	99.38	99.36

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test alert_handler_stress_all_with_rand_reset has 14 failures.
  - 4.alert_handler_stress_all_with_rand_reset.26415418526203385560748771748097036254035343728217315997720822530607077144065
    Line 27266, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 95975837572 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 95975837572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.alert_handler_stress_all_with_rand_reset.40425065759854371750481486971795065764996910942898929528403410361709096678877
    Line 26470, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70085117271 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 70085117271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 2.alert_handler_stress_all_with_rand_reset.27445705489936628104245170261887797476645303131754574405479497853401900828291
    Line 19335, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18223503358 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 18223503358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 5.alert_handler_sig_int_fail.68801632591542431118891457076541206702347437963566888930502797220562841515291
    Line 664, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 2199215250 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 2199215250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_entropy has 1 failures.
  - 20.alert_handler_entropy.68717075546999589285728949838274162820785490064464219914064584272240645831157
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_entropy/latest/run.log
```
  Job ID: smart:cc4ca1f7-8cb7-4110-bbcc-ccfb88cb7ac7
```

ALERT_HANDLER Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9656691e03`