69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.226m | 5.110ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 6.240s | 46.964us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 10.090s | 124.782us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 7.958m | 30.766ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 5.771m | 7.451ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 15.260s | 899.507us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 10.090s | 124.782us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 5.771m | 7.451ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.991m | 27.280ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.045m | 906.999us | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 58.620m | 52.326ms | 49 | 50 | 98.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.145m | 4.051ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.226m | 5.110ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.215m | 4.228ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.216m | 1.128ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.713m | 16.005ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 55.375m | 131.308ms | 49 | 50 | 98.00 |
| alert_handler_lpg_stub_clk | 51.629m | 96.155ms | 49 | 50 | 98.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.188h | 69.133ms | 50 | 50 | 100.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.134m | 1.711ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.220s | 47.498us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.750s | 13.091us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 25.790s | 370.367us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 25.790s | 370.367us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 6.240s | 46.964us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 10.090s | 124.782us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 5.771m | 7.451ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 47.840s | 7.213ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 6.240s | 46.964us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 10.090s | 124.782us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 5.771m | 7.451ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 47.840s | 7.213ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 626 | 630 | 99.37 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.447m | 5.472ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.447m | 5.472ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.447m | 5.472ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.447m | 5.472ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 22.953m | 21.499ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.166m | 3.649ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.166m | 3.649ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.447m | 5.472ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.226m | 5.110ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.226m | 5.110ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.226m | 5.110ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.226m | 5.110ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.145m | 4.051ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 55.375m | 131.308ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.145m | 4.051ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 58.620m | 52.326ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 58.620m | 52.326ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 47.730s | 1.122ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.556h | 187.890ms | 30 | 50 | 60.00 |
| V3 | TOTAL | 30 | 50 | 60.00 | |||
| TOTAL | 826 | 850 | 97.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 11 | 73.33 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.66 | 99.99 | 98.66 | 99.97 | 100.00 | 100.00 | 99.38 | 99.60 |
UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
3.alert_handler_stress_all_with_rand_reset.22889712991335298477615316734852840860241710273734946056856116927808953165339
Line 23945, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 116637822599 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 116637822599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.alert_handler_stress_all_with_rand_reset.101748779070664073721344688496703817489150276100708177289280737005354233515946
Line 48315, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56191629875 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 56191629875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
Test alert_handler_entropy has 1 failures.
7.alert_handler_entropy.40264555853794622477926054261230044105186561229429904854571388645810776632524
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_entropy/latest/run.log
Job ID: smart:95ec20f1-bcbe-468c-b077-be79fe7aaa11
Test alert_handler_lpg_stub_clk has 1 failures.
35.alert_handler_lpg_stub_clk.108257128716447065091061060108240626103937392939371896130344759335923727703077
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:36f1e5d3-9b40-44a3-b3df-d94242f0f33c
Test alert_handler_lpg has 1 failures.
36.alert_handler_lpg.103895403383607362296759967285746538248592903564288480531618986761097834390335
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_lpg/latest/run.log
Job ID: smart:f8ae65a7-9dd5-4430-a5e9-06b8189fc817
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
14.alert_handler_sig_int_fail.52517370099603905491478869868160068605176093812296645008664377829453014930860
Line 417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 117852129 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 117852129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
17.alert_handler_stress_all_with_rand_reset.26763772659686282428527046314655746975051225832213416327102063596056610813292
Line 165408, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 102941214951 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 102941214951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
32.alert_handler_stress_all_with_rand_reset.14101121733702957236450842205939094173220731780335859658453279212440699850088
Line 73761, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18825256702 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 18825256702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---