ALERT_HANDLER Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.131m	4.512ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.220s	855.988us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.300s	259.262us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.917m	4.501ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.982m	4.237ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.610s	900.897us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.300s	259.262us	20	20	100.00
		alert_handler_csr_aliasing	4.982m	4.237ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.721m	21.908ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.273m	5.066ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.152m	279.045ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.305m	4.468ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.131m	4.512ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.160m	1.269ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.365m	2.850ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.650m	123.761ms	49	50	98.00
V2	lpg	alert_handler_lpg	57.407m	237.664ms	49	50	98.00
		alert_handler_lpg_stub_clk	59.374m	230.779ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.260h	91.753ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	43.640s	920.274us	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.440s	53.044us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.480s	25.616us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.200s	763.698us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.200s	763.698us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.220s	855.988us	5	5	100.00
		alert_handler_csr_rw	11.300s	259.262us	20	20	100.00
		alert_handler_csr_aliasing	4.982m	4.237ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.590s	530.343us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.220s	855.988us	5	5	100.00
		alert_handler_csr_rw	11.300s	259.262us	20	20	100.00
		alert_handler_csr_aliasing	4.982m	4.237ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.590s	530.343us	20	20	100.00
V2		TOTAL			624	630	99.05
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.486m	103.252ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.486m	103.252ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.486m	103.252ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.486m	103.252ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.544m	17.656ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
		alert_handler_tl_intg_err	1.306m	1.285ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.306m	1.285ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.486m	103.252ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.131m	4.512ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.131m	4.512ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.131m	4.512ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.131m	4.512ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.305m	4.468ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.407m	237.664ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.305m	4.468ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.152m	279.045ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.152m	279.045ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	20.500s	1.286ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.770h	510.972ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			824	850	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	10	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.62	100.00	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 1.alert_handler_stress_all_with_rand_reset.35805859825043955112422891353771304873179921257161697611174411336862354280020
      Line 13024, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 141377160477 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 141377160477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.88405295016686427602147205302841620005888424300201210131086826178101733912538
      Line 59002, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49794377954 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 49794377954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:

  • Test alert_handler_stress_all_with_rand_reset has 3 failures.

    • 0.alert_handler_stress_all_with_rand_reset.10282810579828631859657352957798774529638952309730273184853937160535223250725
      Line 31059, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 94804583646 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 94804583646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.alert_handler_stress_all_with_rand_reset.76789379606371148021914985133605431003397978753048785451505468559898290825659
      Line 7762, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14407939225 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 14407939225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 5.alert_handler_lpg_stub_clk.86304839179769122583563716369692526589472896619679398728977260379792339687601
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:b895436f-4e70-49cb-89d8-d9db94e2aa6d
      

  • Test alert_handler_entropy has 1 failures.

    • 42.alert_handler_entropy.80406235531521319564710264951013634481748864446740594681341739031238301576217
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_entropy/latest/run.log

        Job ID: smart:1df9bb31-91e6-4da8-9fbd-676dc7701d8c
      

  • Test alert_handler_lpg has 1 failures.

    • 46.alert_handler_lpg.107153737214306939659749042812603144704492845793437608121406434873198957678920
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_lpg/latest/run.log

        Job ID: smart:3bb2717c-7f82-4284-b956-ca05d5339056
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 36.alert_handler_sig_int_fail.79110958368915586267187415393237090769862749179138376056545589064508672982021
      Line 501, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 348626404 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 348626404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 37.alert_handler_stress_all_with_rand_reset.24794069277649720693904688725906169339126913884660658624959829971656039123863
      Line 24528, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12710025012 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 12710025012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 0.alert_handler_sig_int_fail.70053933411284340899594740832231405669460617189079926920733121559617220885969
      Line 665, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  78857369 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (106 [0x6a] vs 105 [0x69]) reg name: alert_handler_reg_block.classc_accum_cnt
        UVM_INFO @  78857369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 34.alert_handler_stress_all_with_rand_reset.14890944338710296640837390738223594629488111100209965491999762158892799998318
      Line 15589, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10747951298 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 10747951298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 44.alert_handler_ping_timeout.66624524052708434186761445217681213407104999604034709590035288789876991695631
      Line 423, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 4693718529 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (372 [0x174] vs 16 [0x10])
        UVM_INFO @ 4693718529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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