349bab6601| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.223m | 6.683ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 9.970s | 102.388us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 11.080s | 248.009us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 4.223m | 5.632ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 2.574m | 4.424ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 15.410s | 169.374us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 11.080s | 248.009us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 2.574m | 4.424ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.651m | 11.346ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.115m | 1.081ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 53.138m | 222.279ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.123m | 1.903ms | 50 | 50 | 100.00 |
| V2 | clk_skew | alert_handler_smoke | 1.223m | 6.683ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.242m | 1.249ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.069m | 1.843ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.634m | 56.526ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 53.420m | 281.522ms | 49 | 50 | 98.00 |
| alert_handler_lpg_stub_clk | 53.113m | 56.724ms | 48 | 50 | 96.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.158h | 69.756ms | 50 | 50 | 100.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 59.560s | 1.514ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 3.990s | 199.372us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.820s | 17.195us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 26.190s | 1.373ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 26.190s | 1.373ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 9.970s | 102.388us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 11.080s | 248.009us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 2.574m | 4.424ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 48.270s | 1.369ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 9.970s | 102.388us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 11.080s | 248.009us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 2.574m | 4.424ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 48.270s | 1.369ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 627 | 630 | 99.52 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.435m | 4.382ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.435m | 4.382ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.435m | 4.382ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.435m | 4.382ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 21.538m | 17.841ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.264m | 1.765ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.264m | 1.765ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.435m | 4.382ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.223m | 6.683ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.223m | 6.683ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.223m | 6.683ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.223m | 6.683ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.123m | 1.903ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 53.420m | 281.522ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.123m | 1.903ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 53.138m | 222.279ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 53.138m | 222.279ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 22.420s | 434.021us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.675h | 266.916ms | 36 | 50 | 72.00 |
| V3 | TOTAL | 36 | 50 | 72.00 | |||
| TOTAL | 833 | 850 | 98.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 13 | 86.67 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.63 | 99.99 | 98.74 | 92.70 | 100.00 | 100.00 | 99.38 | 99.64 |
UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
10.alert_handler_stress_all_with_rand_reset.63546016222487570025591359692248414356401273950058643192178276019169246058417
Line 4373, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7117435752 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7117435752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.alert_handler_stress_all_with_rand_reset.41336761111733091628795362979129928934192481822504127580692359765675081315239
Line 1313, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 962885469 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 962885469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
5.alert_handler_lpg_stub_clk.114012428265544180137084848686353213865667310494616991543477034322264565704394
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:498bc0fb-d148-41b8-aa48-042030bee74e
40.alert_handler_lpg_stub_clk.52160052938199233014381683313521520832415457306775034691039755056669865102902
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:573590b8-0c6c-4880-be31-a839be803899
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:
24.alert_handler_lpg.22776554788584981350165252053798097654758842361315641041627215538238343635307
Line 61654, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_lpg/latest/run.log
UVM_ERROR @ 32525250111 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (377 [0x179] vs 376 [0x178]) reg name: alert_handler_reg_block.classa_accum_cnt
UVM_INFO @ 32525250111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
24.alert_handler_stress_all_with_rand_reset.16973576675758298070742418290467508455871040046680821598071537021439609620270
Line 53325, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 163821985803 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 163821985803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
48.alert_handler_stress_all_with_rand_reset.28173341150054526775042132739106311481321175783495387505415876122877513177763
Line 9283, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35348836350 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 35348836350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---