ALERT_HANDLER Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.010s	102.909us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	11.500s	136.320us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.749m	170.985ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.449m	3.327ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.380s	2.020ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	11.500s	136.320us	20	20	100.00
		alert_handler_csr_aliasing	4.449m	3.327ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.298m	11.326ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.344m	5.450ms	50	50	100.00
V2	entropy	alert_handler_entropy	51.627m	55.772ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	59.530s	3.113ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.006m	4.888ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.306m	8.083ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.412m	60.138ms	50	50	100.00
V2	lpg	alert_handler_lpg	59.118m	200.648ms	49	50	98.00
		alert_handler_lpg_stub_clk	56.369m	116.551ms	48	50	96.00
V2	stress_all	alert_handler_stress_all	1.349h	285.661ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	55.930s	4.770ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.490s	55.632us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.980s	48.593us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.850s	2.745ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.850s	2.745ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.010s	102.909us	5	5	100.00
		alert_handler_csr_rw	11.500s	136.320us	20	20	100.00
		alert_handler_csr_aliasing	4.449m	3.327ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.280s	682.071us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.010s	102.909us	5	5	100.00
		alert_handler_csr_rw	11.500s	136.320us	20	20	100.00
		alert_handler_csr_aliasing	4.449m	3.327ms	5	5	100.00
		alert_handler_same_csr_outstanding	49.280s	682.071us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.288m	23.982ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.288m	23.982ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.288m	23.982ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.288m	23.982ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.930m	126.047ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
		alert_handler_tl_intg_err	1.589m	1.289ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.589m	1.289ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.288m	23.982ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.154m	5.120ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	59.530s	3.113ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	59.118m	200.648ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	59.530s	3.113ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	51.627m	55.772ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	51.627m	55.772ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.740s	980.399us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.613h	705.215ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.71	100.00	100.00	100.00	99.38	99.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test alert_handler_stress_all_with_rand_reset has 14 failures.

    • 3.alert_handler_stress_all_with_rand_reset.11354680560186478518260314949671913123814310768253404014722062176193438416198
      Line 2448, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8469632354 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8469632354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.37591543499378809110413627279551357419664984889399332837341645992855324964163
      Line 12537, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14067842556 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14067842556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* has 1 failures:

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 1.alert_handler_lpg_stub_clk.19618877150357283832971402424690126097475220969342769003196563759246459370175
      Line 7141, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest/run.log

        UVM_ERROR @ 5985634312 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: alert_handler_reg_block.loc_alert_cause_0
        UVM_INFO @ 5985634312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 24.alert_handler_lpg.10357579810048509013458495949789692306294878557268986085575935723149856748538
      Line 63273, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_lpg/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 39.alert_handler_lpg_stub_clk.78307694380238815263382463499075146021681547538436303796398599853946596498213
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:ceea92bb-479a-46e2-88f2-ea0e56202f5e
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 45.alert_handler_stress_all_with_rand_reset.70812486311908973946121700571431406775300177627392828523164690170924902777949
      Line 26909, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33790156557 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 33790156557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.05.17_06.47.12
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