ALERT_HANDLER Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.097m	1.586ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.610s	126.861us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.810s	95.812us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	3.548m	3.711ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.171m	3.387ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.030s	157.837us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.810s	95.812us	20	20	100.00
		alert_handler_csr_aliasing	4.171m	3.387ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.725m	10.959ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.243m	3.945ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.702m	59.030ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.067m	2.534ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.097m	1.586ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.029m	1.089ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.085m	2.340ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.133m	74.547ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.705m	224.927ms	50	50	100.00
		alert_handler_lpg_stub_clk	50.632m	231.127ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.257h	71.424ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	43.770s	11.613ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.750s	110.339us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.140s	28.439us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.420s	2.045ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.420s	2.045ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.610s	126.861us	5	5	100.00
		alert_handler_csr_rw	8.810s	95.812us	20	20	100.00
		alert_handler_csr_aliasing	4.171m	3.387ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.280s	681.609us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.610s	126.861us	5	5	100.00
		alert_handler_csr_rw	8.810s	95.812us	20	20	100.00
		alert_handler_csr_aliasing	4.171m	3.387ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.280s	681.609us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.812m	10.814ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.812m	10.814ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.812m	10.814ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.812m	10.814ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.655m	116.310ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
		alert_handler_tl_intg_err	1.327m	10.442ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.327m	10.442ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.812m	10.814ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.097m	1.586ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.097m	1.586ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.097m	1.586ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.097m	1.586ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.067m	2.534ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.705m	224.927ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.067m	2.534ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.702m	59.030ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.702m	59.030ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	55.200s	1.251ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.616h	631.452ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.71	100.00	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 0.alert_handler_stress_all_with_rand_reset.75016908354262656332010293183643585523153748405345983723439282106800004853360
      Line 10005, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41505487446 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 41505487446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.94252580803552202715162253253109566750707577933289550454253643532849699821824
      Line 27987, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34581488368 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 34581488368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_entropy has 1 failures.

    • 5.alert_handler_entropy.79010439409198871611044159403961218640357364143848316459190171855948243092419
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_entropy/latest/run.log

        Job ID: smart:28fec424-4ab3-4393-9677-38e5873aa115
      

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 14.alert_handler_stress_all_with_rand_reset.36228513887711280576764482157556114007115555820127998404906535696708075410769
      Line 11873, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34439338146 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 34439338146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 23.alert_handler_stress_all_with_rand_reset.22491498022424137158235453114994873477048190605025749243948001995235174587629
      Line 208752, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 100579838690 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
        UVM_INFO @ 100579838690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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