ALERT_HANDLER Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.210m	4.108ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.130s	135.038us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.610s	258.395us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.076m	8.900ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.289m	13.320ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.750s	547.738us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.610s	258.395us	20	20	100.00
		alert_handler_csr_aliasing	4.289m	13.320ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.563m	24.195ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.193m	4.336ms	50	50	100.00
V2	entropy	alert_handler_entropy	59.359m	61.062ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.229m	3.515ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.210m	4.108ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.199m	3.079ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.363m	1.232ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.515m	30.250ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.019m	62.306ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.561m	106.279ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.214h	395.799ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.134m	3.262ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.520s	51.509us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.790s	11.344us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.770s	1.091ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.770s	1.091ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.130s	135.038us	5	5	100.00
		alert_handler_csr_rw	9.610s	258.395us	20	20	100.00
		alert_handler_csr_aliasing	4.289m	13.320ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.060s	728.467us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.130s	135.038us	5	5	100.00
		alert_handler_csr_rw	9.610s	258.395us	20	20	100.00
		alert_handler_csr_aliasing	4.289m	13.320ms	5	5	100.00
		alert_handler_same_csr_outstanding	46.060s	728.467us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.221m	5.664ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.221m	5.664ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.221m	5.664ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.221m	5.664ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.324m	12.860ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
		alert_handler_tl_intg_err	40.690s	2.393ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	40.690s	2.393ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.221m	5.664ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.210m	4.108ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.210m	4.108ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.210m	4.108ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.210m	4.108ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.229m	3.515ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.019m	62.306ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.229m	3.515ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	59.359m	61.062ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	59.359m	61.062ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.031m	1.484ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.631h	110.937ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			826	850	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.67	99.97	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 1.alert_handler_stress_all_with_rand_reset.94527820354254041364843021750120769272443010603070550023228965152269143682707
    Line 29603, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90051481700 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 90051481700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.alert_handler_stress_all_with_rand_reset.96827342737528872467874958345382362999411937491081099164236890606707100489775
    Line 24550, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 191222576315 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 191222576315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 19.alert_handler_stress_all_with_rand_reset.25007602888589994825681130328184279287643537201920661532502322526919785827993
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e545fb4c-6e6a-459f-9967-49009291e518
```
  - 33.alert_handler_stress_all_with_rand_reset.65556825021251037142921476340135825848129116312353894111591597558541855300155
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f7c010c2-f512-4936-a5ee-c4a52ec837af
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 7.alert_handler_stress_all_with_rand_reset.19206527646084305292407784757590168485822629787953479207774013344596364764119
    Line 113629, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28711249733 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 7 [0x7]) reg name: alert_handler_reg_block.classd_state
  UVM_INFO @ 28711249733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 9.alert_handler_stress_all_with_rand_reset.112183894348146017378223197284894193371065465436442074833381796785654141838798
    Line 11873, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17477380764 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17477380764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 25.alert_handler_stress_all.58116413122018507230718876060366071352284064435773968148843837698906256066336
    Line 92630, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 23961132519 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classa_state
  UVM_INFO @ 23961132519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 32.alert_handler_stress_all_with_rand_reset.3254604308422907664647278494239376823591724865258408074432454408521335861839
    Line 109800, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83323580560 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 83323580560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 48.alert_handler_stress_all_with_rand_reset.100404484389020876770883356398484099788137407751056701500509106609849751193644
    Line 1657, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1454211740 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1454211740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1579f6a912`