ALERT_HANDLER Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.314m	5.227ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.290s	635.631us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.460s	321.011us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.012m	77.800ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.653m	4.238ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.060s	898.272us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.460s	321.011us	20	20	100.00
		alert_handler_csr_aliasing	2.653m	4.238ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.958m	5.678ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.208m	4.815ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.735m	114.518ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.181m	4.447ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.314m	5.227ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.233m	1.198ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.268m	5.104ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.752m	32.079ms	50	50	100.00
V2	lpg	alert_handler_lpg	57.831m	70.154ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.499m	112.872ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.248h	294.519ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.109m	1.664ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.810s	134.316us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.920s	18.389us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.400s	1.817ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.400s	1.817ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.290s	635.631us	5	5	100.00
		alert_handler_csr_rw	9.460s	321.011us	20	20	100.00
		alert_handler_csr_aliasing	2.653m	4.238ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.860s	1.372ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.290s	635.631us	5	5	100.00
		alert_handler_csr_rw	9.460s	321.011us	20	20	100.00
		alert_handler_csr_aliasing	2.653m	4.238ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.860s	1.372ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.231m	28.939ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.231m	28.939ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.231m	28.939ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.231m	28.939ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	17.465m	12.399ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
		alert_handler_tl_intg_err	1.532m	1.667ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.532m	1.667ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.231m	28.939ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.314m	5.227ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.314m	5.227ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.314m	5.227ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.314m	5.227ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.181m	4.447ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.831m	70.154ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.181m	4.447ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.735m	114.518ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.735m	114.518ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.730s	627.038us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.722h	110.002ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.78	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 1.alert_handler_stress_all_with_rand_reset.36878775652494915590136561028366189064121618345239047526698506552899122710776
      Line 8602, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15974317906 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 15974317906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.36621468477027805913086853306406793192277330080070667744861103166814877623569
      Line 7094, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22234902917 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22234902917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 36.alert_handler_stress_all_with_rand_reset.37727236338014873579883598295307562820969779738160863030969955571143706118210
      Line 50758, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89075319773 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 89075319773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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