ALERT_HANDLER Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.284m 1.242ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 9.080s 844.879us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 10.210s 503.358us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 6.074m 18.420ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 4.895m 20.950ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 13.450s 573.829us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 10.210s 503.358us 20 20 100.00
alert_handler_csr_aliasing 4.895m 20.950ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 5.353m 22.600ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.203m 1.286ms 50 50 100.00
V2 entropy alert_handler_entropy 51.962m 233.662ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.215m 8.526ms 50 50 100.00
V2 clk_skew alert_handler_smoke 1.284m 1.242ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.203m 3.510ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.096m 955.336us 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 12.149m 16.674ms 50 50 100.00
V2 lpg alert_handler_lpg 57.505m 126.905ms 50 50 100.00
alert_handler_lpg_stub_clk 46.190m 50.420ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.046h 240.169ms 49 50 98.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 1.710m 9.855ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.020s 86.795us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.670s 10.945us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 23.650s 395.173us 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 23.650s 395.173us 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 9.080s 844.879us 5 5 100.00
alert_handler_csr_rw 10.210s 503.358us 20 20 100.00
alert_handler_csr_aliasing 4.895m 20.950ms 5 5 100.00
alert_handler_same_csr_outstanding 44.780s 1.244ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 9.080s 844.879us 5 5 100.00
alert_handler_csr_rw 10.210s 503.358us 20 20 100.00
alert_handler_csr_aliasing 4.895m 20.950ms 5 5 100.00
alert_handler_same_csr_outstanding 44.780s 1.244ms 20 20 100.00
V2 TOTAL 629 630 99.84
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 5.299m 11.263ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 5.299m 11.263ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 5.299m 11.263ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 5.299m 11.263ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 19.510m 18.028ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
alert_handler_tl_intg_err 1.401m 4.775ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.401m 4.775ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 5.299m 11.263ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.284m 1.242ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.284m 1.242ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.284m 1.242ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.284m 1.242ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.215m 8.526ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 57.505m 126.905ms 50 50 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.215m 8.526ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 51.962m 233.662ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 51.962m 233.662ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 53.270s 1.172ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 2.879h 108.730ms 34 50 68.00
V3 TOTAL 34 50 68.00
TOTAL 833 850 98.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 14 93.33
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.67 99.99 98.72 100.00 100.00 100.00 99.38 99.60

Failure Buckets

Past Results