ALERT_HANDLER Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.298m	5.159ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.780s	41.026us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.070s	1.005ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.678m	8.915ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.360m	13.470ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.910s	198.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.070s	1.005ms	20	20	100.00
		alert_handler_csr_aliasing	4.360m	13.470ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.205m	24.197ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.285m	2.340ms	50	50	100.00
V2	entropy	alert_handler_entropy	43.908m	42.971ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	58.090s	4.341ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.298m	5.159ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.172m	4.951ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.155m	1.267ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.036m	12.872ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.556m	231.327ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.920m	58.665ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.177h	72.009ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.357m	4.161ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.980s	101.061us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.770s	14.652us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.220s	4.020ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.220s	4.020ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.780s	41.026us	5	5	100.00
		alert_handler_csr_rw	10.070s	1.005ms	20	20	100.00
		alert_handler_csr_aliasing	4.360m	13.470ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.330s	5.368ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.780s	41.026us	5	5	100.00
		alert_handler_csr_rw	10.070s	1.005ms	20	20	100.00
		alert_handler_csr_aliasing	4.360m	13.470ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.330s	5.368ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.405m	5.483ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.405m	5.483ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.405m	5.483ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.405m	5.483ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.485m	20.653ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
		alert_handler_tl_intg_err	1.420m	7.017ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.420m	7.017ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.405m	5.483ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.298m	5.159ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.298m	5.159ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.298m	5.159ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.298m	5.159ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	58.090s	4.341ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.556m	231.327ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	58.090s	4.341ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	43.908m	42.971ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	43.908m	42.971ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.570s	2.000ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.655h	943.802ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.77	100.00	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
  • Test alert_handler_stress_all_with_rand_reset has 20 failures.

    • 0.alert_handler_stress_all_with_rand_reset.73509203508664982123853133854663717833467608840243839239403524865395597027470
      Line 91769, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 316639698324 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 316639698324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.89902460545781636991977616595162317689034529979165220891798165786335504325314
      Line 11755, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25633317108 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25633317108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

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