ALERT_HANDLER Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.282m	2.735ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.120s	987.928us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.770s	1.216ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.991m	7.825ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.316m	3.460ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.110s	663.551us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.770s	1.216ms	20	20	100.00
		alert_handler_csr_aliasing	4.316m	3.460ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.329m	20.290ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.044m	956.867us	50	50	100.00
V2	entropy	alert_handler_entropy	56.198m	67.516ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.218m	1.123ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.282m	2.735ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.136m	4.096ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.217m	1.085ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	13.219m	70.734ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.719m	255.090ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.200m	112.110ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.023h	245.342ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	57.960s	1.397ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	5.060s	203.804us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.690s	27.253us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.920s	1.744ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.920s	1.744ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.120s	987.928us	5	5	100.00
		alert_handler_csr_rw	10.770s	1.216ms	20	20	100.00
		alert_handler_csr_aliasing	4.316m	3.460ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.720s	667.346us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.120s	987.928us	5	5	100.00
		alert_handler_csr_rw	10.770s	1.216ms	20	20	100.00
		alert_handler_csr_aliasing	4.316m	3.460ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.720s	667.346us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.583m	6.653ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.583m	6.653ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.583m	6.653ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.583m	6.653ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.482m	34.298ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
		alert_handler_tl_intg_err	1.453m	2.442ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.453m	2.442ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.583m	6.653ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.282m	2.735ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.282m	2.735ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.282m	2.735ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.282m	2.735ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.218m	1.123ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.719m	255.090ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.218m	1.123ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.198m	67.516ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.198m	67.516ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	47.970s	1.114ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.635h	214.056ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.99	98.64	100.00	100.00	100.00	99.38	99.40

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test alert_handler_stress_all_with_rand_reset has 15 failures.
  - 0.alert_handler_stress_all_with_rand_reset.21047096485793534108618404795832645655580840756489734484061280287770578164090
    Line 41145, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39241894349 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 39241894349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.alert_handler_stress_all_with_rand_reset.30404303833415092537155389862452848079654666822660293224721402551116373455172
    Line 23772, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 75283006583 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 75283006583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
- Test alert_handler_sig_int_fail has 2 failures.
  - 33.alert_handler_sig_int_fail.44454439855276810520527955429709443341322637363486643445633276417735462043651
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 233649560 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 233649560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.alert_handler_sig_int_fail.30920064995319383701650043244028278272257516747562941282517984293451190079015
    Line 581, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 484360812 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 484360812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 21.alert_handler_stress_all_with_rand_reset.84743611370908305753843076092027575421687500007920358113483001279046089119227
    Line 7259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15056430211 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15056430211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 22.alert_handler_stress_all_with_rand_reset.38319183399544856531228510656615175427165845201129875762521587901588865448201
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5e3d1d40-fd2c-41f5-8a51-6c6e84982603
```

ALERT_HANDLER Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `01a208901a`