ALERT_HANDLER Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.096m	1.249ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.100s	128.237us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.150s	117.690us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.245m	16.098ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.327m	15.340ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.740s	870.950us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.150s	117.690us	20	20	100.00
		alert_handler_csr_aliasing	5.327m	15.340ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.050m	5.148ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.286m	4.770ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.797m	52.267ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.179m	1.252ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.096m	1.249ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.033m	1.923ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.217m	3.042ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.633m	15.671ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.825m	57.253ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.806m	185.695ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.184h	149.181ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	53.010s	2.611ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.890s	40.373us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.940s	42.123us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.770s	302.126us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.770s	302.126us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.100s	128.237us	5	5	100.00
		alert_handler_csr_rw	8.150s	117.690us	20	20	100.00
		alert_handler_csr_aliasing	5.327m	15.340ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.860s	686.827us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.100s	128.237us	5	5	100.00
		alert_handler_csr_rw	8.150s	117.690us	20	20	100.00
		alert_handler_csr_aliasing	5.327m	15.340ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.860s	686.827us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.842m	5.341ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.842m	5.341ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.842m	5.341ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.842m	5.341ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.761m	16.964ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
		alert_handler_tl_intg_err	1.410m	4.634ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.410m	4.634ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.842m	5.341ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.096m	1.249ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.096m	1.249ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.096m	1.249ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.096m	1.249ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.179m	1.252ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.825m	57.253ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.179m	1.252ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.797m	52.267ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.797m	52.267ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	21.530s	341.248us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.957h	355.240ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			833	850	98.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.77	100.00	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test alert_handler_stress_all_with_rand_reset has 10 failures.
  - 3.alert_handler_stress_all_with_rand_reset.74023240991587979906709920840552051267800469086877336187337309765376694658209
    Line 6355, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4702103194 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4702103194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.alert_handler_stress_all_with_rand_reset.22078785038825963751679552591490656617278545524480678659372243305162439145585
    Line 832, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 487469048 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 487469048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 2.alert_handler_stress_all_with_rand_reset.98222795543992049684847909958830281152324072416844592321585995908584233596627
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fcfc1497-00bd-43d7-9c6a-47211e0aa9ee
```
  - 35.alert_handler_stress_all_with_rand_reset.104701484718505823227206819475026377208092006609541416626592792892578566418077
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ee0cab59-38f2-441e-b6f9-0d639c2d6fbc
```
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 12.alert_handler_stress_all_with_rand_reset.63891458872941808235529908307702649824019226696806774737010272943375649782462
    Line 44859, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20195398902 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 20195398902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.alert_handler_stress_all_with_rand_reset.94810576723292124964082451660392050323602441431324177064679232686465986191601
    Line 36850, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29501313052 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 29501313052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 38.alert_handler_sig_int_fail.16246304929584788447146761590479844904930674939453920165812815729700858689354
    Line 335, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  81916963 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @  81916963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 47.alert_handler_sig_int_fail.1879802258272862118771098561565066053177454709553373389418950143745263938602
    Line 418, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 145288781 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 145288781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 48.alert_handler_stress_all_with_rand_reset.69048382987149796158959516256958129221215879538298516102663639188876817086730
    Line 129436, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35804444283 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 35804444283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a182fcef27`