b29ffbb03c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.221m | 2.299ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 8.470s | 102.978us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 8.720s | 471.801us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.538m | 17.495ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.090m | 7.106ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 12.570s | 1.888ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 8.720s | 471.801us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.090m | 7.106ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.582m | 22.158ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.367m | 2.317ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 51.909m | 198.505ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.322m | 12.161ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.221m | 2.299ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.179m | 4.713ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.166m | 4.991ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 12.363m | 319.623ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 58.442m | 777.993ms | 48 | 50 | 96.00 |
| alert_handler_lpg_stub_clk | 53.730m | 381.935ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.113h | 73.558ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.266m | 6.291ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.350s | 97.481us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.930s | 18.768us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 20.220s | 5.675ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 20.220s | 5.675ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 8.470s | 102.978us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 8.720s | 471.801us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.090m | 7.106ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 49.200s | 1.076ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 8.470s | 102.978us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 8.720s | 471.801us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.090m | 7.106ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 49.200s | 1.076ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 626 | 630 | 99.37 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 5.709m | 5.820ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 5.709m | 5.820ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 5.709m | 5.820ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 5.709m | 5.820ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 15.556m | 15.027ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.115m | 904.317us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.115m | 904.317us | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 5.709m | 5.820ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.221m | 2.299ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.221m | 2.299ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.221m | 2.299ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.221m | 2.299ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.322m | 12.161ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 58.442m | 777.993ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.322m | 12.161ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 51.909m | 198.505ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 51.909m | 198.505ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 18.620s | 1.281ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.959h | 474.691ms | 34 | 50 | 68.00 |
| V3 | TOTAL | 34 | 50 | 68.00 | |||
| TOTAL | 830 | 850 | 97.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.68 | 99.99 | 98.70 | 100.00 | 100.00 | 100.00 | 99.38 | 99.68 |
UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
6.alert_handler_stress_all_with_rand_reset.21000467167436731746172155160775353094323750084497545875383199714179155677159
Line 18326, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18810106450 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18810106450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.alert_handler_stress_all_with_rand_reset.103501781371448796715282127025468042333043087119852067389445760859994670381938
Line 43753, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36203261296 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 36203261296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
39.alert_handler_lpg.7076881208494821338946026888315032152450028405834833253085031583609791392204
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_lpg/latest/run.log
Job ID: smart:51b512ff-c344-484a-9ad0-691551a44361
40.alert_handler_lpg.86696708083934163222764817582514455324894591098450954122976498315277589037336
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_lpg/latest/run.log
Job ID: smart:58d22aa4-3fe3-424c-a96d-be990a1ba144
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:
10.alert_handler_stress_all.65064969971018595700162094750867354711096587370348998169523779250540976187433
Line 46546, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 20580125690 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 7 [0x7]) reg name: alert_handler_reg_block.classb_state
UVM_INFO @ 20580125690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
12.alert_handler_sig_int_fail.54742239651570467117639462464707078976682958816072098779228060897980083739280
Line 1486, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 624003924 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 624003924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
14.alert_handler_stress_all_with_rand_reset.71776364579381733143179130467767314734902918659406234801329724148369396460641
Line 23743, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 112902834243 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 112902834243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---