ALERT_HANDLER Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.214m	2.184ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.110s	132.769us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.360s	123.638us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.655m	17.813ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.970m	4.566ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.650s	184.792us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.360s	123.638us	20	20	100.00
		alert_handler_csr_aliasing	4.970m	4.566ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.148m	44.004ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.265m	1.227ms	50	50	100.00
V2	entropy	alert_handler_entropy	48.960m	51.392ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.178m	12.076ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.214m	2.184ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.173m	953.294us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.192m	1.543ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.108m	240.541ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.557m	146.262ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.403m	206.963ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.359h	695.838ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.211m	3.489ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.310s	232.248us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.820s	12.881us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	32.420s	466.321us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	32.420s	466.321us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.110s	132.769us	5	5	100.00
		alert_handler_csr_rw	9.360s	123.638us	20	20	100.00
		alert_handler_csr_aliasing	4.970m	4.566ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.210s	2.813ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.110s	132.769us	5	5	100.00
		alert_handler_csr_rw	9.360s	123.638us	20	20	100.00
		alert_handler_csr_aliasing	4.970m	4.566ms	5	5	100.00
		alert_handler_same_csr_outstanding	51.210s	2.813ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.213m	6.422ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.213m	6.422ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.213m	6.422ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.213m	6.422ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.120m	15.950ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
		alert_handler_tl_intg_err	1.387m	3.694ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.387m	3.694ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.213m	6.422ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.214m	2.184ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.214m	2.184ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.214m	2.184ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.214m	2.184ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.178m	12.076ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.557m	146.262ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.178m	12.076ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	48.960m	51.392ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	48.960m	51.392ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	52.740s	1.165ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.568h	189.439ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.99	98.66	100.00	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test alert_handler_stress_all_with_rand_reset has 16 failures.

    • 1.alert_handler_stress_all_with_rand_reset.26875607709516706390713148202042889012811890378075275814116184512894001940505
      Line 91403, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 172275024956 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 172275024956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.2101135923287693391360021163143891442266956953075796007196515940695745851329
      Line 49950, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 301734664106 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 301734664106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 33.alert_handler_lpg_stub_clk.80929077976302069583878153453267121022853696301342306252753232094653066998390
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:69969dcb-61dc-4ba1-a75d-83d529234eaa
      

  • Test alert_handler_entropy has 1 failures.

    • 47.alert_handler_entropy.85779686212728761725985602174610925759446195652133674442154935682508303150396
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_entropy/latest/run.log

        Job ID: smart:7c3a8e2b-8816-47c6-8605-22b40fb5e3dc
      

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 44.alert_handler_stress_all_with_rand_reset.64382879390595193291616954224218590861097782850198492620072631600939731017293
      Line 3663, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3606591964 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3606591964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.06.06_11.19.13
• 2024.06.05_04.15.29
• 2024.06.03_07.14.22
• 2024.05.31_05.05.47
• 2024.05.29_03.38.18
• 2024.05.27_04.42.51