302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.070m | 909.082us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 5.990s | 358.795us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 9.680s | 451.568us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 3.652m | 14.815ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.523m | 8.291ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 15.240s | 201.227us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 9.680s | 451.568us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.523m | 8.291ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.579m | 21.978ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.346m | 5.034ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 48.808m | 48.390ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.150m | 1.048ms | 50 | 50 | 100.00 |
| V2 | clk_skew | alert_handler_smoke | 1.070m | 909.082us | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.196m | 6.061ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.507m | 8.011ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.616m | 30.516ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 55.529m | 223.901ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 52.748m | 84.969ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.057h | 134.031ms | 48 | 50 | 96.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 57.170s | 5.295ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.100s | 130.100us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.940s | 25.344us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 29.300s | 1.045ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 29.300s | 1.045ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 5.990s | 358.795us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.680s | 451.568us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.523m | 8.291ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 43.160s | 648.166us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 5.990s | 358.795us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.680s | 451.568us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.523m | 8.291ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 43.160s | 648.166us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 628 | 630 | 99.68 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.180m | 6.472ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.180m | 6.472ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.180m | 6.472ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.180m | 6.472ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 22.592m | 17.293ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.086m | 8.849ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.086m | 8.849ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.180m | 6.472ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.070m | 909.082us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.070m | 909.082us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.070m | 909.082us | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.070m | 909.082us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.150m | 1.048ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 55.529m | 223.901ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.150m | 1.048ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 48.808m | 48.390ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 48.808m | 48.390ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 1.172m | 1.706ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.715h | 193.682ms | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 833 | 850 | 98.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 14 | 93.33 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.67 | 99.99 | 98.69 | 100.00 | 100.00 | 100.00 | 99.38 | 99.64 |
UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
0.alert_handler_stress_all_with_rand_reset.78624385094725361814858661351706982871009539222613383170275821701606102535582
Line 83028, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 123888351880 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123888351880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.alert_handler_stress_all_with_rand_reset.72730270651331330980625240228472118111116554606739874050196790421923849215191
Line 50723, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23988011443 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23988011443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
8.alert_handler_stress_all_with_rand_reset.24193851172074754131767813776349062805373930462838080044719042727353037563948
Line 2623, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 776371322 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 776371322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.alert_handler_stress_all_with_rand_reset.6045426880936351663081045716365618560698137335804176181717626383905532519253
Line 143080, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 241486020580 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 241486020580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
2.alert_handler_stress_all.22567933358141696960388319317798322176291394894138393162313826106490304696353
Line 583, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 995323180 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 995323180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:
6.alert_handler_stress_all.111500655760321012992772237667586439680729145417992390397986172228185227673405
Line 85489, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 15203553583 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 7 [0x7]) reg name: alert_handler_reg_block.classd_state
UVM_INFO @ 15203553583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
28.alert_handler_stress_all_with_rand_reset.26861595496340069744769118488311764342199960320620987010586511278393044937392
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest/run.log
Job ID: smart:703d0639-d062-48f0-89df-368b700a0f52