f92a5ee77b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.288m | 1.373ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 8.720s | 104.119us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 9.070s | 196.550us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 6.777m | 29.657ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.645m | 4.658ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 13.100s | 604.593us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 9.070s | 196.550us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.645m | 4.658ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 5.702m | 5.964ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 52.370s | 7.768ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 54.424m | 395.303ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 57.480s | 9.619ms | 50 | 50 | 100.00 |
| V2 | clk_skew | alert_handler_smoke | 1.288m | 1.373ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.219m | 2.232ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.069m | 4.929ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 10.082m | 30.780ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 44.706m | 199.481ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 43.784m | 186.143ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.044h | 274.418ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.212m | 14.777ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.140s | 802.120us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 2.010s | 24.254us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 26.910s | 439.146us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 26.910s | 439.146us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 8.720s | 104.119us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.070s | 196.550us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.645m | 4.658ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 41.800s | 690.896us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 8.720s | 104.119us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.070s | 196.550us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.645m | 4.658ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 41.800s | 690.896us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 629 | 630 | 99.84 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.659m | 7.222ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.659m | 7.222ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.659m | 7.222ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.659m | 7.222ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 20.340m | 40.740ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.120m | 3.680ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.120m | 3.680ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.659m | 7.222ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.288m | 1.373ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.288m | 1.373ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.288m | 1.373ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.288m | 1.373ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 57.480s | 9.619ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 44.706m | 199.481ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 57.480s | 9.619ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 54.424m | 395.303ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 54.424m | 395.303ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 27.770s | 625.589us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 2.306h | 96.115ms | 27 | 50 | 54.00 |
| V3 | TOTAL | 27 | 50 | 54.00 | |||
| TOTAL | 826 | 850 | 97.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 14 | 93.33 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 98.63 | 99.99 | 98.72 | 92.67 | 100.00 | 100.00 | 99.38 | 99.64 |
UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
1.alert_handler_stress_all_with_rand_reset.109159964980623176448490215080786537559932152205070843782393541985226384212468
Line 3147, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12307477770 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12307477770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.alert_handler_stress_all_with_rand_reset.26967736942285732024415294383996694375898325206112566264679811955203512348323
Line 50132, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43483212975 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 43483212975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
13.alert_handler_stress_all_with_rand_reset.49787253497568080283270377389810302074024000369724808896474095045268503305996
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a3a3a8ea-83ca-4630-8b20-d2db8131092f
44.alert_handler_stress_all_with_rand_reset.57782892218507112437591803616799217746259338333232054783998000801443464239584
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log
Job ID: smart:da86651e-07cd-44ed-afd0-9c71106c70c5
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:
16.alert_handler_stress_all_with_rand_reset.99008895109528327732693009835229194433670774301639626517774474223362108510676
Line 146817, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 98206604857 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 98206604857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.alert_handler_stress_all_with_rand_reset.1488592238822245696536125827131505958933433122057376249641902548037844572769
Line 35785, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 125869857452 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 125869857452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
3.alert_handler_stress_all.99933291128467649699827597171937827118116339701725561877404212909635096892205
Line 88252, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 98863004377 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 98863004377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
29.alert_handler_stress_all_with_rand_reset.65409168277424102976297159213017891836313134164579906054059152407089238986489
Line 7958, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16901984161 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 16901984161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---