ALERT_HANDLER Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.535m	1.369ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.840s	487.902us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.350s	500.606us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.627m	10.299ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.423m	3.970ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.630s	1.244ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.350s	500.606us	20	20	100.00
		alert_handler_csr_aliasing	4.423m	3.970ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.440m	103.311ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.141m	1.337ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.386m	123.244ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.141m	4.044ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.535m	1.369ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.042m	4.303ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.345m	2.476ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.655m	91.778ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.069m	185.233ms	50	50	100.00
		alert_handler_lpg_stub_clk	59.762m	248.927ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.101h	70.634ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.136m	6.910ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.270s	914.075us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.890s	18.924us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	34.240s	1.960ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	34.240s	1.960ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.840s	487.902us	5	5	100.00
		alert_handler_csr_rw	9.350s	500.606us	20	20	100.00
		alert_handler_csr_aliasing	4.423m	3.970ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.100s	1.386ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.840s	487.902us	5	5	100.00
		alert_handler_csr_rw	9.350s	500.606us	20	20	100.00
		alert_handler_csr_aliasing	4.423m	3.970ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.100s	1.386ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.365m	6.377ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.365m	6.377ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.365m	6.377ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.365m	6.377ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.392m	250.912ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
		alert_handler_tl_intg_err	1.346m	4.976ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.346m	4.976ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.365m	6.377ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.535m	1.369ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.535m	1.369ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.535m	1.369ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.535m	1.369ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.141m	4.044ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.069m	185.233ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.141m	4.044ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.386m	123.244ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.386m	123.244ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	42.120s	1.337ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.033h	166.305ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.75	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 5.alert_handler_stress_all_with_rand_reset.3654613759680695464094353819866684383908318526224710058323581250011391198881
      Line 7197, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27640283602 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27640283602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.alert_handler_stress_all_with_rand_reset.26236623531621488961701279502370032735124177674197914278784401766300269519614
      Line 1962, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23053717766 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10029 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23053717766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 4.alert_handler_stress_all_with_rand_reset.26389637619840896092080504301184196258148416164492039330991981177115164948031
      Line 38109, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 313953571054 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 313953571054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.alert_handler_stress_all_with_rand_reset.110128373393835008847488292303363491946211746565530556531392684534119964277127
      Line 43424, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 761984520701 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 761984520701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 26.alert_handler_stress_all_with_rand_reset.35338886061061142879055099730471878752316995017241552025689825878323956378217
      Line 46400, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23638203905 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 23638203905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.06.10_07.03.33
• 2024.06.08_13.25.19
• 2024.06.07_05.09.12
• 2024.06.06_11.19.13
• 2024.06.05_04.15.29
• 2024.06.03_07.14.22