ALERT_HANDLER Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.172m	4.722ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.800s	103.840us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.550s	130.402us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.933m	34.223ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.538m	24.821ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.880s	770.666us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.550s	130.402us	20	20	100.00
		alert_handler_csr_aliasing	4.538m	24.821ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.215m	23.648ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.144m	4.347ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.101m	227.924ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.179m	1.341ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.172m	4.722ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.194m	11.821ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.113m	997.258us	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.128m	55.911ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.963m	316.205ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.317m	51.133ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.201h	108.243ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	57.550s	5.865ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.210s	99.429us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.650s	10.668us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	25.480s	442.546us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	25.480s	442.546us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.800s	103.840us	5	5	100.00
		alert_handler_csr_rw	10.550s	130.402us	20	20	100.00
		alert_handler_csr_aliasing	4.538m	24.821ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.130s	1.677ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.800s	103.840us	5	5	100.00
		alert_handler_csr_rw	10.550s	130.402us	20	20	100.00
		alert_handler_csr_aliasing	4.538m	24.821ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.130s	1.677ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.337m	5.706ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.337m	5.706ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.337m	5.706ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.337m	5.706ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	17.856m	54.795ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
		alert_handler_tl_intg_err	1.513m	2.576ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.513m	2.576ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.337m	5.706ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.172m	4.722ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.172m	4.722ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.172m	4.722ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.172m	4.722ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.179m	1.341ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.963m	316.205ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.179m	1.341ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.101m	227.924ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.101m	227.924ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	42.640s	1.073ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.517h	91.957ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.76	100.00	100.00	100.00	99.38	99.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test alert_handler_stress_all_with_rand_reset has 15 failures.

    • 2.alert_handler_stress_all_with_rand_reset.99772043612344150224493666525030001030855900995708902176175282639796425728721
      Line 13657, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13352772355 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13352772355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.16874364093380394067330068411108526386058922236513927079849883301248366668799
      Line 9356, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13082777146 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13082777146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 9.alert_handler_stress_all_with_rand_reset.75055139550765968781009304438875055773319162096280134241479859292860099705440
      Line 46865, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12259140880 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 12259140880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.alert_handler_stress_all_with_rand_reset.33533262275508083788830764171283725161409467071380255367615900202728398447905
      Line 911, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1360193316 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1360193316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_entropy has 1 failures.

    • 29.alert_handler_entropy.104882872813472872135408619979034339989167842505022790862983367590944788960225
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_entropy/latest/run.log

        Job ID: smart:4f4705e9-80d1-4d55-965b-29d4091d530b
      

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