ALERT_HANDLER Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.156m	2.431ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.850s	244.868us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.160s	1.248ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.186m	10.826ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.004m	7.688ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.520s	200.953us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.160s	1.248ms	20	20	100.00
		alert_handler_csr_aliasing	3.004m	7.688ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.832m	56.780ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.362m	1.289ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.744m	121.884ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.192m	2.003ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.156m	2.431ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.285m	4.738ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.257m	2.014ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.601m	17.570ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.145m	61.221ms	50	50	100.00
		alert_handler_lpg_stub_clk	58.415m	246.439ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.076h	68.698ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	54.720s	1.235ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.420s	53.039us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.870s	18.857us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.010s	345.662us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.010s	345.662us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.850s	244.868us	5	5	100.00
		alert_handler_csr_rw	10.160s	1.248ms	20	20	100.00
		alert_handler_csr_aliasing	3.004m	7.688ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.790s	1.446ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.850s	244.868us	5	5	100.00
		alert_handler_csr_rw	10.160s	1.248ms	20	20	100.00
		alert_handler_csr_aliasing	3.004m	7.688ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.790s	1.446ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.061m	14.240ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.061m	14.240ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.061m	14.240ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.061m	14.240ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.232m	34.827ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
		alert_handler_tl_intg_err	1.370m	2.834ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.370m	2.834ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.061m	14.240ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.156m	2.431ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.156m	2.431ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.156m	2.431ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.156m	2.431ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.192m	2.003ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.145m	61.221ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.192m	2.003ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.744m	121.884ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.744m	121.884ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.840s	538.531us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.681h	414.870ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.68	99.99	98.70	100.00	100.00	100.00	99.38	99.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
  • Test alert_handler_stress_all_with_rand_reset has 19 failures.

    • 1.alert_handler_stress_all_with_rand_reset.85769810688769382446401490255025176647918486533861394572268386466121812354258
      Line 439, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 107940404 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 107940404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.alert_handler_stress_all_with_rand_reset.27440385229911286111418045934145808175383351939260931612976241975148205879407
      Line 9946, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30837574569 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 30837574569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 0.alert_handler_stress_all_with_rand_reset.22200580273098195024749360283235339516947179816518658673782811935341961300272
      Line 26506, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 253735884268 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 253735884268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.alert_handler_stress_all_with_rand_reset.73334514870400796688410660915602732072830458811379709822839627513377425079007
      Line 71991, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 280438453056 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 280438453056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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