ALERT_HANDLER Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.039m	4.576ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.400s	43.450us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.750s	490.961us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.679m	22.838ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.202m	4.856ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	11.940s	585.633us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.750s	490.961us	20	20	100.00
		alert_handler_csr_aliasing	5.202m	4.856ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.936m	121.394ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.145m	10.857ms	50	50	100.00
V2	entropy	alert_handler_entropy	52.778m	208.798ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.001m	953.011us	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.039m	4.576ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.191m	1.248ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.108m	5.792ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.294m	14.973ms	49	50	98.00
V2	lpg	alert_handler_lpg	54.887m	108.936ms	50	50	100.00
		alert_handler_lpg_stub_clk	48.828m	189.744ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.108h	71.785ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	59.740s	1.579ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.440s	101.433us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.600s	11.026us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.420s	1.090ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.420s	1.090ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.400s	43.450us	5	5	100.00
		alert_handler_csr_rw	9.750s	490.961us	20	20	100.00
		alert_handler_csr_aliasing	5.202m	4.856ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.380s	5.398ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.400s	43.450us	5	5	100.00
		alert_handler_csr_rw	9.750s	490.961us	20	20	100.00
		alert_handler_csr_aliasing	5.202m	4.856ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.380s	5.398ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.628m	5.139ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.628m	5.139ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.628m	5.139ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.628m	5.139ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.279m	17.146ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
		alert_handler_tl_intg_err	1.447m	1.302ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.447m	1.302ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.628m	5.139ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.039m	4.576ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.039m	4.576ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.039m	4.576ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.039m	4.576ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.001m	953.011us	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.887m	108.936ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.001m	953.011us	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	52.778m	208.798ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	52.778m	208.798ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	55.760s	1.355ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	1.996h	915.192ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.69	99.99	98.77	100.00	100.00	100.00	99.38	99.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

  • Test alert_handler_stress_all_with_rand_reset has 14 failures.

    • 1.alert_handler_stress_all_with_rand_reset.8110870377767635340086035311760107743434331109367125814807215627290365093595
      Line 91378, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20917410646 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20917410646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.105732066809888689485488656965903979346448804935212704874793106978018273436255
      Line 467, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 221302977 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 221302977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:

  • Test alert_handler_stress_all_with_rand_reset has 3 failures.

    • 22.alert_handler_stress_all_with_rand_reset.23225756485919410151926204115216053547201881787110901459284652671571634240463
      Line 31955, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110266440907 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 110266440907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.alert_handler_stress_all_with_rand_reset.18988708144240320543497013728010830031888226602908270981069604357413018862569
      Line 34953, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51210300069 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 51210300069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 16.alert_handler_ping_timeout.86576110375049203586567992566602317030779899451876403742017074998748410376682
      Line 424, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 3943377104 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (44 [0x2c] vs 57 [0x39])
        UVM_INFO @ 3943377104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 46.alert_handler_sig_int_fail.46724138550757033896113820509017791923136771051997936385093463066396352605185
      Line 582, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  67874232 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 6 [0x6]) reg name: alert_handler_reg_block.classa_state
        UVM_INFO @  67874232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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