ALERT_HANDLER Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.126m	1.023ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.270s	104.794us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.720s	234.636us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.344m	34.236ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.238m	19.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.780s	290.933us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.720s	234.636us	20	20	100.00
		alert_handler_csr_aliasing	5.238m	19.009ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.653m	41.449ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.006m	4.272ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.800m	508.215ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.269m	4.917ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.126m	1.023ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	56.930s	3.845ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.224m	11.570ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.089m	16.498ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.993m	62.794ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.705m	212.278ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	58.178m	59.317ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.014m	5.664ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.940s	53.069us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.800s	29.294us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.410s	423.917us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.410s	423.917us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.270s	104.794us	5	5	100.00
		alert_handler_csr_rw	8.720s	234.636us	20	20	100.00
		alert_handler_csr_aliasing	5.238m	19.009ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.510s	1.389ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.270s	104.794us	5	5	100.00
		alert_handler_csr_rw	8.720s	234.636us	20	20	100.00
		alert_handler_csr_aliasing	5.238m	19.009ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.510s	1.389ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.626m	7.118ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.626m	7.118ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.626m	7.118ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.626m	7.118ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.752m	69.305ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
		alert_handler_tl_intg_err	1.356m	1.346ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.356m	1.346ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.626m	7.118ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.126m	1.023ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.126m	1.023ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.126m	1.023ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.126m	1.023ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.269m	4.917ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.993m	62.794ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.269m	4.917ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.800m	508.215ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.800m	508.215ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.860s	2.159ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.471h	81.086ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			837	850	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.69	99.97	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:

  • Test alert_handler_stress_all_with_rand_reset has 11 failures.

    • 7.alert_handler_stress_all_with_rand_reset.21308909223187892598956424731040465308397857784466090632134656416951588199332
      Line 1342, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3134623954 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3134623954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.alert_handler_stress_all_with_rand_reset.19184723399956415353380284041754128812194371205403969567409393565593952802627
      Line 6343, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4774300960 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4774300960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 20.alert_handler_stress_all.24572153493948850456553708713996779608958820429698766573356439069367351110292
      Line 94278, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 102660966048 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 102660966048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 42.alert_handler_stress_all_with_rand_reset.11221049062109840932997519535162553027031092456558641625824639855572836394980
      Line 26504, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45032712653 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 45032712653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.06.22_11.50.49
• 2024.06.14_07.36.06
• 2024.06.12_05.11.42
• 2024.06.11_12.11.41
• 2024.06.10_07.03.33
• 2024.06.08_13.25.19