ALERT_HANDLER Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.126m	1.167ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.810s	247.771us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.790s	518.812us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.251m	30.046ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	2.830m	1.203ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.810s	1.827ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.790s	518.812us	20	20	100.00
		alert_handler_csr_aliasing	2.830m	1.203ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.836m	19.927ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.240m	5.448ms	50	50	100.00
V2	entropy	alert_handler_entropy	53.025m	112.602ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.188m	4.496ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.126m	1.167ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.128m	1.183ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.158m	5.049ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.708m	161.728ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.377m	53.959ms	50	50	100.00
		alert_handler_lpg_stub_clk	55.660m	218.663ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.221h	127.978ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	33.910s	757.466us	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.160s	45.815us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.670s	11.226us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	14.530s	101.900us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	14.530s	101.900us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.810s	247.771us	5	5	100.00
		alert_handler_csr_rw	10.790s	518.812us	20	20	100.00
		alert_handler_csr_aliasing	2.830m	1.203ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.780s	2.743ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.810s	247.771us	5	5	100.00
		alert_handler_csr_rw	10.790s	518.812us	20	20	100.00
		alert_handler_csr_aliasing	2.830m	1.203ms	5	5	100.00
		alert_handler_same_csr_outstanding	50.780s	2.743ms	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.730m	22.999ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.730m	22.999ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.730m	22.999ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.730m	22.999ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	22.044m	66.507ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
		alert_handler_tl_intg_err	1.721m	4.294ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.721m	4.294ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.730m	22.999ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.126m	1.167ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.126m	1.167ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.126m	1.167ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.126m	1.167ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.188m	4.496ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.377m	53.959ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.188m	4.496ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	53.025m	112.602ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	53.025m	112.602ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	26.520s	470.470us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.425h	427.947ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			834	850	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.99	98.69	100.00	100.00	100.00	99.38	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

  • Test alert_handler_stress_all_with_rand_reset has 13 failures.

    • 1.alert_handler_stress_all_with_rand_reset.5577516043661236273388961606095029689997924814966001608487640543615379371639
      Line 420, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 898888591 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 898888591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.114203599344010548715713020635876994771341401062458635585819984333742257049163
      Line 13051, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25377225986 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25377225986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 30.alert_handler_stress_all.57540119790753380332169308339381044652228737049925507431688705929361549769218
      Line 1077, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 273666149 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 273666149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 36.alert_handler_stress_all_with_rand_reset.89655180730744985575834475047934404489642542537327745961476369257464444816018
      Line 155125, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 123618283208 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 123618283208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 38.alert_handler_stress_all.97463141559223930782509996131684123216791852150421517117187995400566597227447
      Line 79599, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 52215992531 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 52215992531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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